A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET
This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.29-42 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Kim, Jihwan Balankutty, Ajay Dokania, Rajeev K. Elshazly, Amr Kim, Hyung Seok Kundu, Sandipan Shi, Dan Weaver, Skyler Yu, Kai O'Mahony, Frank |
| description | This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment \pi -coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm 2 . |
| doi_str_mv | 10.1109/JSSC.2018.2874040 |
| format | Article |
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Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment <inline-formula> <tex-math notation="LaTeX">\pi </tex-math></inline-formula>-coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm 2 .</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2018.2874040</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>10 nm ; 4:1 serializer ; <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">π -coil ; Bandwidth ; Circuits ; Clocks ; Coils ; Delays ; Diodes ; Error correction ; Error detection ; feed-forward equalizer (FFE) ; FinFET ; four-level pulse-amplitude modulation (PAM-4) ; Modulation ; Optical signal processing ; Phase locked loops ; Phase locked systems ; Pulse amplitude modulation ; Pulse generation ; pulse generator ; quarter-rate ; Reconfiguration ; SerDes ; transmitter (TX)</subject><ispartof>IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.29-42</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-12c6e807a801a32962608781a34ddd91b6a137860b2333fd98be0ba26c29e7a13</citedby><cites>FETCH-LOGICAL-c293t-12c6e807a801a32962608781a34ddd91b6a137860b2333fd98be0ba26c29e7a13</cites><orcidid>0000-0003-0805-2692 ; 0000-0002-5599-2997 ; 0000-0002-0628-9138</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8500752$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8500752$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kim, Jihwan</creatorcontrib><creatorcontrib>Balankutty, Ajay</creatorcontrib><creatorcontrib>Dokania, Rajeev K.</creatorcontrib><creatorcontrib>Elshazly, Amr</creatorcontrib><creatorcontrib>Kim, Hyung Seok</creatorcontrib><creatorcontrib>Kundu, Sandipan</creatorcontrib><creatorcontrib>Shi, Dan</creatorcontrib><creatorcontrib>Weaver, Skyler</creatorcontrib><creatorcontrib>Yu, Kai</creatorcontrib><creatorcontrib>O'Mahony, Frank</creatorcontrib><title>A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment <inline-formula> <tex-math notation="LaTeX">\pi </tex-math></inline-formula>-coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm 2 .</description><subject>10 nm</subject><subject>4:1 serializer</subject><subject><italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">π -coil</subject><subject>Bandwidth</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Coils</subject><subject>Delays</subject><subject>Diodes</subject><subject>Error correction</subject><subject>Error detection</subject><subject>feed-forward equalizer (FFE)</subject><subject>FinFET</subject><subject>four-level pulse-amplitude modulation (PAM-4)</subject><subject>Modulation</subject><subject>Optical signal processing</subject><subject>Phase locked loops</subject><subject>Phase locked systems</subject><subject>Pulse amplitude modulation</subject><subject>Pulse generation</subject><subject>pulse generator</subject><subject>quarter-rate</subject><subject>Reconfiguration</subject><subject>SerDes</subject><subject>transmitter (TX)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtOwzAQRS0EEqXwAYiNJdZpZ-zEcZZVRQqoPNQGgbqxnMShqdqk2OmCv8dVKlbzuPfOSIeQW4QRIiTj5-VyOmKAcsRkHEIIZ2SAUSQDjPnXORmAl4KEAVySK-c2fgxDiQOymlBERmf52NH3yUsQ0kj00-tiRRemaJuq_j5YnW8Nzaxu3K7uOmPpZ92taba2xgSZ3tM0faB1QxGCZkfTukkfsmtyUemtMzenOiQffjt9DOZvs6fpZB4ULOFdgKwQRkKsJaDmLBFMgIyl78OyLBPMhUYeSwE545xXZSJzA7lmwsdN7LUhue_v7m37czCuU5v2YBv_UjEUSShAxIl3Ye8qbOucNZXa23qn7a9CUEeE6ohQHRGqE0KfuesztTHm3y8jgDhi_A-1I2bu</recordid><startdate>201901</startdate><enddate>201901</enddate><creator>Kim, Jihwan</creator><creator>Balankutty, Ajay</creator><creator>Dokania, Rajeev K.</creator><creator>Elshazly, Amr</creator><creator>Kim, Hyung Seok</creator><creator>Kundu, Sandipan</creator><creator>Shi, Dan</creator><creator>Weaver, Skyler</creator><creator>Yu, Kai</creator><creator>O'Mahony, Frank</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0805-2692</orcidid><orcidid>https://orcid.org/0000-0002-5599-2997</orcidid><orcidid>https://orcid.org/0000-0002-0628-9138</orcidid></search><sort><creationdate>201901</creationdate><title>A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET</title><author>Kim, Jihwan ; Balankutty, Ajay ; Dokania, Rajeev K. ; Elshazly, Amr ; Kim, Hyung Seok ; Kundu, Sandipan ; Shi, Dan ; Weaver, Skyler ; Yu, Kai ; O'Mahony, Frank</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-12c6e807a801a32962608781a34ddd91b6a137860b2333fd98be0ba26c29e7a13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>10 nm</topic><topic>4:1 serializer</topic><topic><italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">π -coil</topic><topic>Bandwidth</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Coils</topic><topic>Delays</topic><topic>Diodes</topic><topic>Error correction</topic><topic>Error detection</topic><topic>feed-forward equalizer (FFE)</topic><topic>FinFET</topic><topic>four-level pulse-amplitude modulation (PAM-4)</topic><topic>Modulation</topic><topic>Optical signal processing</topic><topic>Phase locked loops</topic><topic>Phase locked systems</topic><topic>Pulse amplitude modulation</topic><topic>Pulse generation</topic><topic>pulse generator</topic><topic>quarter-rate</topic><topic>Reconfiguration</topic><topic>SerDes</topic><topic>transmitter (TX)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kim, Jihwan</creatorcontrib><creatorcontrib>Balankutty, Ajay</creatorcontrib><creatorcontrib>Dokania, Rajeev K.</creatorcontrib><creatorcontrib>Elshazly, Amr</creatorcontrib><creatorcontrib>Kim, Hyung Seok</creatorcontrib><creatorcontrib>Kundu, Sandipan</creatorcontrib><creatorcontrib>Shi, Dan</creatorcontrib><creatorcontrib>Weaver, Skyler</creatorcontrib><creatorcontrib>Yu, Kai</creatorcontrib><creatorcontrib>O'Mahony, Frank</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, Jihwan</au><au>Balankutty, Ajay</au><au>Dokania, Rajeev K.</au><au>Elshazly, Amr</au><au>Kim, Hyung Seok</au><au>Kundu, Sandipan</au><au>Shi, Dan</au><au>Weaver, Skyler</au><au>Yu, Kai</au><au>O'Mahony, Frank</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2019-01</date><risdate>2019</risdate><volume>54</volume><issue>1</issue><spage>29</spage><epage>42</epage><pages>29-42</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment <inline-formula> <tex-math notation="LaTeX">\pi </tex-math></inline-formula>-coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm 2 .</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2874040</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0003-0805-2692</orcidid><orcidid>https://orcid.org/0000-0002-5599-2997</orcidid><orcidid>https://orcid.org/0000-0002-0628-9138</orcidid></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.29-42 |
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| subjects | 10 nm 4:1 serializer <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">π -coil Bandwidth Circuits Clocks Coils Delays Diodes Error correction Error detection feed-forward equalizer (FFE) FinFET four-level pulse-amplitude modulation (PAM-4) Modulation Optical signal processing Phase locked loops Phase locked systems Pulse amplitude modulation Pulse generation pulse generator quarter-rate Reconfiguration SerDes transmitter (TX) |
| title | A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET |
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