$A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 \times Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration$

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 \times Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

A 6-bit 2.5-GS/s 8\times dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolat...

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE journal of solid-state circuits 2019-01, Vol.54 (1), p.288-297
Hauptverfasser:	Oh, Dong-Ryeol, Kim, Jong-In, Jo, Dong-Shin, Kim, Woo-Chul, Chang, Dong-Jin, Ryu, Seung-Tak
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog-digital conversion Analog-to-digital conversion (ADC) Calibration Capacitance cascaded phase interpolation (PI) flash ADC Interpolation interpolation ADC Latches offset calibration Power demand Time-domain analysis time-domain interpolation (TDI) voltage-to-time conversion (VTC)
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