A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS

This paper presents a 2 GHz digital-to-time converter (DTC) with 244 fs time resolution. The DTC consists of a multi-modulus divider (MMD) and a phase interpolator (PI) as coarse and fine tuning blocks, respectively. Control logic is implemented to prevent shoot-through current during the interpolat...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2016-12, Vol.51 (12), p.2992-3004
Hauptverfasser:	Sievert, Sebastian, Degani, Ofir, Ben-Bassat, Assaf, Banin, Rotem, Ravi, Ashoke, Thomann, Wolfgang, Klepser, Bernd-Ulrich, Boos, Zdravko, Schmitt-Landsiedel, Doris
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer architecture Delays Digital-to-phase converter digital-to-time converter DNL DPC DTC edge interpolator INL Interpolation Jitter Linearity phase interpolator Signal resolution Tuning
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