Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE cir...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2016-04, Vol.51 (4), p.871-880
Hauptverfasser:	Jaeduk Han, Yue Lu, Sutardja, Nicholas, Kwangmo Jung, Alon, Elad
Format:	Artikel
Sprache:	eng
Schlagworte:	Chip-to-chip communication Clocks current integration decision feedback equalizer (DFE) Decision feedback equalizers feedforward equalizer (FFE) high-speed links Latches Linearity Logic gates Receivers
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