A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS
This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed,...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2016-03, Vol.51 (3), p.587-597 |
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| container_end_page | 597 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Haoyu Qian Qiyuan Liu Silva-Martinez, Jose Hoyos, Sebastian |
| description | This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc. |
| doi_str_mv | 10.1109/JSSC.2015.2510026 |
| format | Article |
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The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2015.2510026</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Baseband ; CMOS integrated circuits ; CMOS RF PA ; CMOS RF power amplifier ; CMOS transmitter ; Gain ; highly efficient PA ; highly linear PA ; linear power amplifier ; Power generation ; Radio frequency ; RF transmitter ; segmented PA ; Switches ; Timing</subject><ispartof>IEEE journal of solid-state circuits, 2016-03, Vol.51 (3), p.587-597</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c363t-2c3c78eb33c8ed85a263f0d24886f9a41f02cde585e4cb15ccb8fbb621efd7ed3</citedby><cites>FETCH-LOGICAL-c363t-2c3c78eb33c8ed85a263f0d24886f9a41f02cde585e4cb15ccb8fbb621efd7ed3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7409962$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7409962$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Haoyu Qian</creatorcontrib><creatorcontrib>Qiyuan Liu</creatorcontrib><creatorcontrib>Silva-Martinez, Jose</creatorcontrib><creatorcontrib>Hoyos, Sebastian</creatorcontrib><title>A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.</description><subject>Baseband</subject><subject>CMOS integrated circuits</subject><subject>CMOS RF PA</subject><subject>CMOS RF power amplifier</subject><subject>CMOS transmitter</subject><subject>Gain</subject><subject>highly efficient PA</subject><subject>highly linear PA</subject><subject>linear power amplifier</subject><subject>Power generation</subject><subject>Radio frequency</subject><subject>RF transmitter</subject><subject>segmented PA</subject><subject>Switches</subject><subject>Timing</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFZ_gHgZEI-JO_uRbI411FaptFBFwcOy2Www1SbtJkH015vS4mmYl-edgYeQS6QhIk1uH5fLNGQUZcgkUsqiIzJAKVWAMX87JgNKUQUJo_SUnDXNql-FUDgg7yPgEvK7Ncy7dtO1sKi_nQdT5cBVn8OsrJzxMDFlBYsRvJbtBwgRJjewcOazj8ZgWsAwgcn0F3pIUKjWkD7Nl-fkpDBfjbs4zCF5uR8_p9NgNp88pKNZYHnE24BZbmPlMs6tcrmShkW8oDkTSkVFYgQWlNncSSWdsBlKazNVZFnE0BV57HI-JNf7uxtfbzvXtHpVd77qX2qMVcwUspj2FO4p6-um8a7QG1-ujf_RSPXOod451DuH-uCw71ztO6Vz7p-PBU2SiPE_b5dnFQ</recordid><startdate>20160301</startdate><enddate>20160301</enddate><creator>Haoyu Qian</creator><creator>Qiyuan Liu</creator><creator>Silva-Martinez, Jose</creator><creator>Hoyos, Sebastian</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20160301</creationdate><title>A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS</title><author>Haoyu Qian ; Qiyuan Liu ; Silva-Martinez, Jose ; Hoyos, Sebastian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c363t-2c3c78eb33c8ed85a263f0d24886f9a41f02cde585e4cb15ccb8fbb621efd7ed3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Baseband</topic><topic>CMOS integrated circuits</topic><topic>CMOS RF PA</topic><topic>CMOS RF power amplifier</topic><topic>CMOS transmitter</topic><topic>Gain</topic><topic>highly efficient PA</topic><topic>highly linear PA</topic><topic>linear power amplifier</topic><topic>Power generation</topic><topic>Radio frequency</topic><topic>RF transmitter</topic><topic>segmented PA</topic><topic>Switches</topic><topic>Timing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Haoyu Qian</creatorcontrib><creatorcontrib>Qiyuan Liu</creatorcontrib><creatorcontrib>Silva-Martinez, Jose</creatorcontrib><creatorcontrib>Hoyos, Sebastian</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Haoyu Qian</au><au>Qiyuan Liu</au><au>Silva-Martinez, Jose</au><au>Hoyos, Sebastian</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2016-03-01</date><risdate>2016</risdate><volume>51</volume><issue>3</issue><spage>587</spage><epage>597</epage><pages>587-597</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched ON and OFF according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2015.2510026</doi><tpages>11</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2016-03, Vol.51 (3), p.587-597 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Baseband CMOS integrated circuits CMOS RF PA CMOS RF power amplifier CMOS transmitter Gain highly efficient PA highly linear PA linear power amplifier Power generation Radio frequency RF transmitter segmented PA Switches Timing |
| title | A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS |
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