A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation

This paper presents a highly configurable low-voltage write-ability assist implementation along with a sense-amplifier offset reduction technique to improve SRAM read performance. Write-assist implementation combines negative bit-line (BL) and VDD collapse schemes in an efficient way to maximize Vmi...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2016-02, Vol.51 (2), p.557-567
Hauptverfasser:	Sinangil, Mahmut E., Poulton, John W., Fojtik, Matthew R., Greer, Thomas H., Tell, Stephen G., Gotterba, Andreas J., Wang, Jesse, Golbus, Jason, Zimmer, Brian, Dally, William J., Gray, C. Thomas
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitors CMOS CMOS integrated circuits Failure analysis low-voltage SRAM offset compensation Random access memory SRAM assist Timing Transistors Voltage control
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