$A 6.7 MHz to 1.24 GHz \text\;^}} Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS$

A 6.7 MHz to 1.24 GHz \text\;^}} Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS

In this paper, an all-digital delay-locked loop (ADDLL) with a phase-tracing delay unit (PTDU) has been proposed to achieve wide-operating frequency range, low power, and low cost. For the wide-range DLL, the long delay line is replaced by a PTDU which includes two gated ring oscillators (GROs) for...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2016-02, Vol.51 (2), p.412-427
Hauptverfasser:	Hsieh, Min-Han, Chen, Liang-Hsin, Liu, Shen-Iuan, Chen, Charlie Chung-Ping
Format:	Artikel
Sprache:	eng
Schlagworte:	All-digital Delay lines delay-locked loop (DLL) fast locking Jitter Logic gates open-loop locking phase-tracing delay unit (PTDU) Power demand Radiation detectors wide range
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