Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

This paper presents highly reliable reference bitline bias designs for 64 Mb and 128 Mb chain FeRAM™. The hysteresis shape deformation of ferroelectric capacitor due to temperature variation causes cell signal level shifts of both "1" and "0" data. The reference bitline bias of 6...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2015-05, Vol.50 (5), p.1324-1331
Hauptverfasser:	Ogiwara, Ryu, Takashima, Daisaburo, Doumae, Sumiko, Shiratake, Shinichiro, Takizawa, Ryousuke, Shiga, Hidehiro
Format:	Artikel
Sprache:	eng
Schlagworte:	BGR FeRAM Ferroelectric films ferroelectric memory hysteresis Nonvolatile memory Product introduction Random access memory reference voltage Semiconductor device measurement Temperature Temperature distribution Temperature measurement Voltage measurement
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