A 14 nm FinFET 128 Mb SRAM With V Enhancement Techniques for Low-Power Applications

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 μm 2 and a 0.080 μm 2 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve VMIN of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a wri...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2015-01, Vol.50 (1), p.158-169
Hauptverfasser:	Song, Taejoong, Rim, Woojin, Jung, Jonghoon, Yang, Giyong, Park, Jaeho, Park, Sunghyun, Kim, Yongho, Baek, Kang-Hyun, Baek, Sanghoon, Oh, Sang-Kyu, Jung, Jinsuk, Kim, Sungbong, Kim, Gyuhong, Kim, Jintae, Lee, Youngkeun, Sim, Sang-Pil, Yoon, Jong Shik, Choi, Kyu-Myung, Won, Hyosig, Park, Jaehong
Format:	Artikel
Sprache:	eng
Schlagworte:	14 nm FinFET assist Circuit stability Disturbance-noise reduction FinFETs low-power low-voltage Noise Random access memory SRAM System-on-chip Timing
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