Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the h...

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Veröffentlicht in:IEEE journal of solid-state circuits 2013-04, Vol.48 (4), p.924-931
Hauptverfasser: Miyano, S., Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Sakurai, T., Shinohara, H.
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Sprache:eng
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