A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

We propose low-leakage current embedded SRAMs with high-performance for mobile applications. The proposed SRAM has two standby modes depending on temperature; one is a low-voltage resume-standby mode to reduce the standby current (I STBY ) more effectively at room temperature, and the other is the conventional resume-standby to reduce I STBY effectively at high temperature. These schemes are implemented in a single SRAM macro with an all-digital current comparator (ADCC) that chooses either mode by monitoring I STBY automatically. ADCC has a time to digital converter (TDC) which is suitable for leakage measurement. Moreover, the proposed monitoring sequence can compensate the error of the measurement caused by the variation of the MOSFETs. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 kb SRAM achieves 0.41 μA standby leakage which is half of the conventional value. This SRAM also realizes a high-speed operation with an access time of 420 ps.