A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS
This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integra...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2012-12, Vol.47 (12), p.3220-3231 |
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| creator | Agrawal, A. Bulzacchelli, J. F. Dickson, T. O. Liu, Y. Tierno, J. A. Friedman, D. J. |
| description | This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm 2 and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz. |
| doi_str_mv | 10.1109/JSSC.2012.2216412 |
| format | Article |
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F. ; Dickson, T. O. ; Liu, Y. ; Tierno, J. A. ; Friedman, D. J.</creator><creatorcontrib>Agrawal, A. ; Bulzacchelli, J. F. ; Dickson, T. O. ; Liu, Y. ; Tierno, J. A. ; Friedman, D. J.</creatorcontrib><description>This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm 2 and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2012.2216412</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Analog multiplication ; Applied sciences ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; CMOS integrated circuits ; current-integrating summer ; Decision feedback equalizers ; decision-feedback equalizer (DFE) ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; feed-forward equalizer (FFE) ; Feedforward systems ; Integrated circuits ; receive-side FFE (RX-FFE) ; receiver ; Receivers ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm 2 and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.</description><subject>Analog multiplication</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>CMOS integrated circuits</subject><subject>current-integrating summer</subject><subject>Decision feedback equalizers</subject><subject>decision-feedback equalizer (DFE)</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>feed-forward equalizer (FFE)</subject><subject>Feedforward systems</subject><subject>Integrated circuits</subject><subject>receive-side FFE (RX-FFE)</subject><subject>receiver</subject><subject>Receivers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>serial link</subject><subject>Transceivers</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE9PAjEUxBujiYh-AOOlF49d-vpn2x5xZRGDIXExejDZdEs3VmEhWzTx27sI4fImk5l5hx9C10ATAGoGj0WRJYwCSxiDVAA7QT2QUhNQ_O0U9SgFTQyj9BxdxPjZWSE09ND7EIMh42oQceHbYJd4Gpov_OydDz--xa9h-4Hv1t0RZG43OM9H2DYLLP_dfefy78Ztw7qJODRYSNKscDGb4OxpVlyis9ouo786aB-95KN59kCms_EkG06JY0ZuieIg6wqoZYqlC24rIbXTotZUSaMWVFLufepq04mqLTjnqeZO-opqYQTlfQT7v65dx9j6uty0YWXb3xJoucNT7vCUOzzlAU-3ud1vNjY6u6xb27gQj0OWasm1UV3vZt8L3vtjnHKmuBL8D67naPI</recordid><startdate>20121201</startdate><enddate>20121201</enddate><creator>Agrawal, A.</creator><creator>Bulzacchelli, J. F.</creator><creator>Dickson, T. O.</creator><creator>Liu, Y.</creator><creator>Tierno, J. A.</creator><creator>Friedman, D. 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J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-7315fb10a2726d3ab458c84f807597d0503ee6cf93ee7fa1cce083c5eb0849403</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Analog multiplication</topic><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>CMOS integrated circuits</topic><topic>current-integrating summer</topic><topic>Decision feedback equalizers</topic><topic>decision-feedback equalizer (DFE)</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>feed-forward equalizer (FFE)</topic><topic>Feedforward systems</topic><topic>Integrated circuits</topic><topic>receive-side FFE (RX-FFE)</topic><topic>receiver</topic><topic>Receivers</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>serial link</topic><topic>Transceivers</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Agrawal, A.</creatorcontrib><creatorcontrib>Bulzacchelli, J. F.</creatorcontrib><creatorcontrib>Dickson, T. O.</creatorcontrib><creatorcontrib>Liu, Y.</creatorcontrib><creatorcontrib>Tierno, J. A.</creatorcontrib><creatorcontrib>Friedman, D. J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Agrawal, A.</au><au>Bulzacchelli, J. F.</au><au>Dickson, T. O.</au><au>Liu, Y.</au><au>Tierno, J. A.</au><au>Friedman, D. J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2012-12-01</date><risdate>2012</risdate><volume>47</volume><issue>12</issue><spage>3220</spage><epage>3231</epage><pages>3220-3231</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm 2 and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2012.2216412</doi><tpages>12</tpages></addata></record> |
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| subjects | Analog multiplication Applied sciences Circuit properties Circuits of signal characteristics conditioning (including delay circuits) CMOS integrated circuits current-integrating summer Decision feedback equalizers decision-feedback equalizer (DFE) Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology feed-forward equalizer (FFE) Feedforward systems Integrated circuits receive-side FFE (RX-FFE) receiver Receivers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices serial link Transceivers |
| title | A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS |
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