A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalize...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE journal of solid-state circuits 2012-03, Vol.47 (3), p.627-640
Hauptverfasser:	CHEN, Ming-Shuan, SHIH, Yu-Nan, LIN, Chen-Lun, HUNG, Hao-Wei, LEE, Jri
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Bandwidth Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Clock and data recovery (CDR) Clocks CMOS integrated circuits Delay Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics equalizer Exact sciences and technology Finite impulse response filter finite-inpulse response (FIR) filter Frequency filters Integrated circuits majority voting Miscellaneous Power transmission lines Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices transceiver (TRx) Transceivers
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!