A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2011-11, Vol.46 (11), p.2713-2726 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Teman, A. Pergament, L. Cohen, O. Fish, A. |
| description | Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power. |
| doi_str_mv | 10.1109/JSSC.2011.2164009 |
| format | Article |
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As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2011.2164009</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Arrays ; Circuit properties ; Circuits ; CMOS memory integrated circuits ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electric potential ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Feedback ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; leakage suppression ; Low voltage ; MOS devices ; Noise ; Random access memory ; Semiconductor electronics. Microelectronics. Optoelectronics. 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As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.</description><subject>Applied sciences</subject><subject>Arrays</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>CMOS memory integrated circuits</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric potential</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Feedback</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>leakage suppression</subject><subject>Low voltage</subject><subject>MOS devices</subject><subject>Noise</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>SRAM</subject><subject>Static random access memory</subject><subject>Steady-state</subject><subject>Threshold voltage</subject><subject>Transistors</subject><subject>ultra low power</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkFtLAzEQhYMoWKs_QHwJgqgPWzO5bLKPpbReqChuK76FbJqFtnupSUvpv3eXlj74NDPMdw4zB6FrID0Akjy9pemgRwlAj0LMCUlOUAeEUBFI9nOKOoSAihJKyDm6CGHRjJwr6KBhH1NBcPmNFV5mmBNclXharL2JxvUWf9Zb53EywelmtSp2eOTcLDN2idOv_jt-SEdR2zxeorPcFMFdHWoXTUfDyeAlGn88vw7648gywdeRiR2njHEb51ywWQJUWsgUJ7FtZkEtUw2Y00xKSV0iGVc2nnHJSJbNpJCsi-73vitf_25cWOtyHqwrClO5ehN0EjOlmKTQkLf_yEW98VVznE6AcSEEbyHYQ9bXIXiX65Wfl8bvNBDdxqrbWHUbqz7E2mjuDsYmWFPk3lR2Ho5CyqVQsvmyi2723Nw5d1zHhCgBnP0BxN55Eg</recordid><startdate>20111101</startdate><enddate>20111101</enddate><creator>Teman, A.</creator><creator>Pergament, L.</creator><creator>Cohen, O.</creator><creator>Fish, A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20111101</creationdate><title>A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)</title><author>Teman, A. ; Pergament, L. ; Cohen, O. ; Fish, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c354t-a6e42334c6f453d9127c1b8406c45352c38c35f2b7772e97348c6d4730bbd7573</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Applied sciences</topic><topic>Arrays</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>CMOS memory integrated circuits</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electric potential</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Feedback</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>leakage suppression</topic><topic>Low voltage</topic><topic>MOS devices</topic><topic>Noise</topic><topic>Random access memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>SRAM</topic><topic>Static random access memory</topic><topic>Steady-state</topic><topic>Threshold voltage</topic><topic>Transistors</topic><topic>ultra low power</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Teman, A.</creatorcontrib><creatorcontrib>Pergament, L.</creatorcontrib><creatorcontrib>Cohen, O.</creatorcontrib><creatorcontrib>Fish, A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Teman, A.</au><au>Pergament, L.</au><au>Cohen, O.</au><au>Fish, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2011-11-01</date><risdate>2011</risdate><volume>46</volume><issue>11</issue><spage>2713</spage><epage>2726</epage><pages>2713-2726</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. 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| ispartof | IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2713-2726 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Arrays Circuit properties Circuits CMOS memory integrated circuits Design. Technologies. Operation analysis. Testing Digital circuits Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Feedback Integrated circuits Integrated circuits by function (including memories and processors) leakage suppression Low voltage MOS devices Noise Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SRAM Static random access memory Steady-state Threshold voltage Transistors ultra low power Voltage |
| title | A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM) |
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