A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2011-03, Vol.46 (3), p.627-638 |
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| container_end_page | 638 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 46 |
| creator | Zanuso, M Levantino, S Samori, C Lacaita, A L |
| description | A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm 2 . |
| doi_str_mv | 10.1109/JSSC.2010.2104270 |
| format | Article |
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The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm 2 .</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2010.2104270</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>adaptive filter ; ADPLL ; Applied sciences ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; DCO ; Delay ; Delay lines ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; DPLL ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; fractional-N ; frequency synthesis ; Integrated circuits ; jitter ; LMS ; Modulation ; Noise ; Oscillators, resonators, synthetizers ; Phase locked loops ; phase noise ; Quantization ; SDR ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; spur ; TDC ; Topology</subject><ispartof>IEEE journal of solid-state circuits, 2011-03, Vol.46 (3), p.627-638</ispartof><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c210t-5065b318408f4437fed7da09228c3d64978c86157028db47a2306097ccaafc643</citedby><cites>FETCH-LOGICAL-c210t-5065b318408f4437fed7da09228c3d64978c86157028db47a2306097ccaafc643</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5708187$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5708187$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=23938243$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Zanuso, M</creatorcontrib><creatorcontrib>Levantino, S</creatorcontrib><creatorcontrib>Samori, C</creatorcontrib><creatorcontrib>Lacaita, A L</creatorcontrib><title>A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm 2 .</description><subject>adaptive filter</subject><subject>ADPLL</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>DCO</subject><subject>Delay</subject><subject>Delay lines</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>DPLL</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>fractional-N</subject><subject>frequency synthesis</subject><subject>Integrated circuits</subject><subject>jitter</subject><subject>LMS</subject><subject>Modulation</subject><subject>Noise</subject><subject>Oscillators, resonators, synthetizers</subject><subject>Phase locked loops</subject><subject>phase noise</subject><subject>Quantization</subject><subject>SDR</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>spur</subject><subject>TDC</subject><subject>Topology</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1OwzAUhC0EEqVwAMTGG5Ypzz-JnWUV6A-KoFJBsItcx6FBIYnsgATn4Abcp2fCUaCrp9H7ZjQahM4JTAiB-Op2vU4mFLykBDgVcIBGJAxlQAR7PkQjACKDmAIcoxPnXr3kXJIRaqb4qczNRtU5ZpMIzxdf-Lp8KTtV4d337gfPrNJd2dSqCu7wKk093m3xaqucwcu6M7ZtKtUD3vbhkyzuo_4j1u27xYmqtakG6hQdFapy5uzvjtHj7OYhWQTp_XyZTNNA-_5dEEIUbhiRHGTBOROFyUWuIKZUapZHPBZSy4iEAqjMN1woyiCCWGitVKEjzsaIDLnaNs5ZU2StLd-U_cwIZP1iWb9Y1i-W_S3mPZeDp1VOq6qwvnfp9kbKYiYpZ567GLjSGLN_-y6SSMF-AbG3c7o</recordid><startdate>201103</startdate><enddate>201103</enddate><creator>Zanuso, M</creator><creator>Levantino, S</creator><creator>Samori, C</creator><creator>Lacaita, A L</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201103</creationdate><title>A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation</title><author>Zanuso, M ; Levantino, S ; Samori, C ; Lacaita, A L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c210t-5065b318408f4437fed7da09228c3d64978c86157028db47a2306097ccaafc643</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>adaptive filter</topic><topic>ADPLL</topic><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>DCO</topic><topic>Delay</topic><topic>Delay lines</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>DPLL</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>fractional-N</topic><topic>frequency synthesis</topic><topic>Integrated circuits</topic><topic>jitter</topic><topic>LMS</topic><topic>Modulation</topic><topic>Noise</topic><topic>Oscillators, resonators, synthetizers</topic><topic>Phase locked loops</topic><topic>phase noise</topic><topic>Quantization</topic><topic>SDR</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>spur</topic><topic>TDC</topic><topic>Topology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zanuso, M</creatorcontrib><creatorcontrib>Levantino, S</creatorcontrib><creatorcontrib>Samori, C</creatorcontrib><creatorcontrib>Lacaita, A L</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zanuso, M</au><au>Levantino, S</au><au>Samori, C</au><au>Lacaita, A L</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2011-03</date><risdate>2011</risdate><volume>46</volume><issue>3</issue><spage>627</spage><epage>638</epage><pages>627-638</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm 2 .</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2010.2104270</doi><tpages>12</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | adaptive filter ADPLL Applied sciences Circuit properties Circuits of signal characteristics conditioning (including delay circuits) DCO Delay Delay lines Design. Technologies. Operation analysis. Testing Digital circuits DPLL Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology fractional-N frequency synthesis Integrated circuits jitter LMS Modulation Noise Oscillators, resonators, synthetizers Phase locked loops phase noise Quantization SDR Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices spur TDC Topology |
| title | A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation |
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