A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2007-02, Vol.42 (2), p.361-373 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | YANG, Rong-Jyi LIU, Shen-Iuan |
| description | A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively |
| doi_str_mv | 10.1109/JSSC.2006.889381 |
| format | Article |
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The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. 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(IEEE) 2007</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c493t-4ee04a4ab71e1c334ec179298b2ae558ce18dbf8095ff43a6338f04c6bcda4213</citedby><cites>FETCH-LOGICAL-c493t-4ee04a4ab71e1c334ec179298b2ae558ce18dbf8095ff43a6338f04c6bcda4213</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4077181$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4077181$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18474337$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>YANG, Rong-Jyi</creatorcontrib><creatorcontrib>LIU, Shen-Iuan</creatorcontrib><title>A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively</description><subject>Added delay</subject><subject>ADDLL</subject><subject>Algorithms</subject><subject>Applied sciences</subject><subject>Approximation</subject><subject>Approximation algorithms</subject><subject>Balancing</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Counting circuits</subject><subject>DCC</subject><subject>Delay lines</subject><subject>delay-locked loop (DLL)</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>edge combine</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Frequency</subject><subject>Hardware</subject><subject>harmonic lock</subject><subject>Integrated circuits</subject><subject>Jitter</subject><subject>Mathematical analysis</subject><subject>Registers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>successive approximation register (SAR)</subject><subject>Synchronous</subject><subject>variable successive approximation register (VSAR)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kcGLUzEQxoO4YF29C16CIHpJN_OS95IcS9e1ShfBuuot5KXzatb0pSbtYf3rTemisAdPwzC_75sZPkJeAJ8CcHPxcbWaTxvOu6nWRmh4RCbQtpqBEt8fkwnnoJmp8yfkaSm3tZVSw4R8m1HJWdtyer34TRcub9MYPLvKiHQWI7sMm7B3kV5idHdsmfxPXNNlSjt6U8K4oY5-dTm4PiJdzT5XySblsP-xfUbOBhcLPr-v5-Tm6t2X-YItP73_MJ8tmZdG7JlE5NJJ1ytA8EJI9KBMY3TfOKznewS97gfNTTsMUrhOCD1w6bver51sQJyTNyffXU6_Dlj2dhuKxxjdiOlQrOGiazptTCXf_peETkGjDPC2oq8eoLfpkMf6hzXQgIK2O27mJ8jnVErGwe5y2Lp8Z4HbYyT2GIk9RmJPkVTJ63tfV7yLQ3ajD-WfTkslhVCVe3niAiL-HUuuFFSXP9c6kGY</recordid><startdate>20070201</startdate><enddate>20070201</enddate><creator>YANG, Rong-Jyi</creator><creator>LIU, Shen-Iuan</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20070201</creationdate><title>A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm</title><author>YANG, Rong-Jyi ; LIU, Shen-Iuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c493t-4ee04a4ab71e1c334ec179298b2ae558ce18dbf8095ff43a6338f04c6bcda4213</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Added delay</topic><topic>ADDLL</topic><topic>Algorithms</topic><topic>Applied sciences</topic><topic>Approximation</topic><topic>Approximation algorithms</topic><topic>Balancing</topic><topic>Circuit properties</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Counting circuits</topic><topic>DCC</topic><topic>Delay lines</topic><topic>delay-locked loop (DLL)</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>edge combine</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Frequency</topic><topic>Hardware</topic><topic>harmonic lock</topic><topic>Integrated circuits</topic><topic>Jitter</topic><topic>Mathematical analysis</topic><topic>Registers</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>successive approximation register (SAR)</topic><topic>Synchronous</topic><topic>variable successive approximation register (VSAR)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>YANG, Rong-Jyi</creatorcontrib><creatorcontrib>LIU, Shen-Iuan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANG, Rong-Jyi</au><au>LIU, Shen-Iuan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2007-02-01</date><risdate>2007</risdate><volume>42</volume><issue>2</issue><spage>361</spage><epage>373</epage><pages>361-373</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18mum CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40MHz to 550MHz without the harmonic-locking issue. It dissipates 12.6mW from a 1.8V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550MHz are 1.5ps and 12ps, respectively</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2006.889381</doi><tpages>13</tpages><oa>free_for_read</oa></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2007-02, Vol.42 (2), p.361-373 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Added delay ADDLL Algorithms Applied sciences Approximation Approximation algorithms Balancing Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Clocks CMOS CMOS technology Counting circuits DCC Delay lines delay-locked loop (DLL) Design. Technologies. Operation analysis. Testing edge combine Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency Hardware harmonic lock Integrated circuits Jitter Mathematical analysis Registers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices successive approximation register (SAR) Synchronous variable successive approximation register (VSAR) |
| title | A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm |
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