A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-/spl mu/m CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.