A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1986-08, Vol.21 (4), p.505-513 |
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| Hauptverfasser: | , |
| Format: | Artikel |
| Sprache: | eng |
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| container_end_page | 513 |
|---|---|
| container_issue | 4 |
| container_start_page | 505 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 21 |
| creator | Hatamian, M. Cash, G.L. |
| description | |
| doi_str_mv | 10.1109/JSSC.1986.1052564 |
| format | Article |
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| fulltext | fulltext |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1986-08, Vol.21 (4), p.505-513 |
| issn | 0018-9200 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_JSSC_1986_1052564 |
| source | IEEE Electronic Library (IEL) |
| title | A 70-MHz 8-bit×8-bit parallel pipelined multiplier in 2.5-μm CMOS |
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