An area-efficient approach to the design of very-large time constants in switched-capacitor integrators

A switched-capacitor integrator circuit with very high time constant using capacitive T-cells, is presented. According to a set of design equations and constraints, a test circuit previously needing an excessive capacitive ratio of over 700 has been integrated with a capacitance spread of only 25. C...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1984-10, Vol.19 (5), p.772-780
Hauptverfasser:	Sansen, W.M.C., Van Peteghem, P.M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Area measurement Capacitance Circuit properties Circuit testing Clocks Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy consumption Equations Exact sciences and technology Integrated circuit measurements Power amplifiers Power measurement Switching circuits
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