A gigabit MOS logic circuit with buried channel MOSFETs

An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depl...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1980-10, Vol.15 (5), p.809-816
Hauptverfasser:	Nishiuchi, K., Shibayama, H., Nakamura, T., Hisatsugu, T., Ishikawa, H., Fukukawa, Y.
Format:	Artikel
Sprache:	eng
Schlagworte:	Capacitance Delay effects Driver circuits Feedback circuits Inverters Logic circuits MOSFETs Scattering Transconductance Voltage
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container_end_page	816
container_issue	5
container_start_page	809
container_title	IEEE journal of solid-state circuits
container_volume	15
creator	Nishiuchi, K. Shibayama, H. Nakamura, T. Hisatsugu, T. Ishikawa, H. Fukukawa, Y.
description	An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.
doi_str_mv	10.1109/JSSC.1980.1051475
format	Article
fullrecord	<record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_JSSC_1980_1051475</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1051475</ieee_id><sourcerecordid>28889040</sourcerecordid><originalsourceid>FETCH-LOGICAL-c356t-4a149dc0cab011dd8358c99dbe5a99b1a8dc8b5a659b088c4577bbd6e30e6f9e3</originalsourceid><addsrcrecordid>eNqNkD9PwzAUxC0EEqXwARBLJrYUv9iO7bGqoICKOhQkNsv_2hqlTbETIb49idKBDaanu_e7Gw6ha8ATACzvnler2QSk6CRmQDk7QSNgTOTAyfspGmEMIpcFxufoIqWPTlIqYIT4NNuEjTahyV6Wq6yqN8FmNkTbds5XaLaZaWPwLrNbvd_7qqce7l_TJTpb6yr5q-Mdo7fOnj3mi-X8aTZd5JawssmpBiqdxVYbDOCcIExYKZ3xTEtpQAtnhWG6ZNJgISxlnBvjSk-wL9fSkzG6HXoPsf5sfWrULiTrq0rvfd0mVQghJKb4H2BRkoKTv0HCC0nKvhEG0MY6pejX6hDDTsdvBVj1o6t-dNWPro6jd5mbIRO897_44fsDbKN7_w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>23729360</pqid></control><display><type>article</type><title>A gigabit MOS logic circuit with buried channel MOSFETs</title><source>IEEE Electronic Library (IEL)</source><creator>Nishiuchi, K. ; Shibayama, H. ; Nakamura, T. ; Hisatsugu, T. ; Ishikawa, H. ; Fukukawa, Y.</creator><creatorcontrib>Nishiuchi, K. ; Shibayama, H. ; Nakamura, T. ; Hisatsugu, T. ; Ishikawa, H. ; Fukukawa, Y.</creatorcontrib><description>An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.1980.1051475</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Delay effects ; Driver circuits ; Feedback circuits ; Inverters ; Logic circuits ; MOSFETs ; Scattering ; Transconductance ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1980-10, Vol.15 (5), p.809-816</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c356t-4a149dc0cab011dd8358c99dbe5a99b1a8dc8b5a659b088c4577bbd6e30e6f9e3</citedby><cites>FETCH-LOGICAL-c356t-4a149dc0cab011dd8358c99dbe5a99b1a8dc8b5a659b088c4577bbd6e30e6f9e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1051475$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1051475$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nishiuchi, K.</creatorcontrib><creatorcontrib>Shibayama, H.</creatorcontrib><creatorcontrib>Nakamura, T.</creatorcontrib><creatorcontrib>Hisatsugu, T.</creatorcontrib><creatorcontrib>Ishikawa, H.</creatorcontrib><creatorcontrib>Fukukawa, Y.</creatorcontrib><title>A gigabit MOS logic circuit with buried channel MOSFETs</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.</description><subject>Capacitance</subject><subject>Delay effects</subject><subject>Driver circuits</subject><subject>Feedback circuits</subject><subject>Inverters</subject><subject>Logic circuits</subject><subject>MOSFETs</subject><subject>Scattering</subject><subject>Transconductance</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1980</creationdate><recordtype>article</recordtype><recordid>eNqNkD9PwzAUxC0EEqXwARBLJrYUv9iO7bGqoICKOhQkNsv_2hqlTbETIb49idKBDaanu_e7Gw6ha8ATACzvnler2QSk6CRmQDk7QSNgTOTAyfspGmEMIpcFxufoIqWPTlIqYIT4NNuEjTahyV6Wq6yqN8FmNkTbds5XaLaZaWPwLrNbvd_7qqce7l_TJTpb6yr5q-Mdo7fOnj3mi-X8aTZd5JawssmpBiqdxVYbDOCcIExYKZ3xTEtpQAtnhWG6ZNJgISxlnBvjSk-wL9fSkzG6HXoPsf5sfWrULiTrq0rvfd0mVQghJKb4H2BRkoKTv0HCC0nKvhEG0MY6pejX6hDDTsdvBVj1o6t-dNWPro6jd5mbIRO897_44fsDbKN7_w</recordid><startdate>19801001</startdate><enddate>19801001</enddate><creator>Nishiuchi, K.</creator><creator>Shibayama, H.</creator><creator>Nakamura, T.</creator><creator>Hisatsugu, T.</creator><creator>Ishikawa, H.</creator><creator>Fukukawa, Y.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><scope>7SP</scope><scope>7U5</scope></search><sort><creationdate>19801001</creationdate><title>A gigabit MOS logic circuit with buried channel MOSFETs</title><author>Nishiuchi, K. ; Shibayama, H. ; Nakamura, T. ; Hisatsugu, T. ; Ishikawa, H. ; Fukukawa, Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c356t-4a149dc0cab011dd8358c99dbe5a99b1a8dc8b5a659b088c4577bbd6e30e6f9e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1980</creationdate><topic>Capacitance</topic><topic>Delay effects</topic><topic>Driver circuits</topic><topic>Feedback circuits</topic><topic>Inverters</topic><topic>Logic circuits</topic><topic>MOSFETs</topic><topic>Scattering</topic><topic>Transconductance</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Nishiuchi, K.</creatorcontrib><creatorcontrib>Shibayama, H.</creatorcontrib><creatorcontrib>Nakamura, T.</creatorcontrib><creatorcontrib>Hisatsugu, T.</creatorcontrib><creatorcontrib>Ishikawa, H.</creatorcontrib><creatorcontrib>Fukukawa, Y.</creatorcontrib><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nishiuchi, K.</au><au>Shibayama, H.</au><au>Nakamura, T.</au><au>Hisatsugu, T.</au><au>Ishikawa, H.</au><au>Fukukawa, Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A gigabit MOS logic circuit with buried channel MOSFETs</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1980-10-01</date><risdate>1980</risdate><volume>15</volume><issue>5</issue><spage>809</spage><epage>816</epage><pages>809-816</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.1980.1051475</doi><tpages>8</tpages></addata></record>
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subjects	Capacitance Delay effects Driver circuits Feedback circuits Inverters Logic circuits MOSFETs Scattering Transconductance Voltage
title	A gigabit MOS logic circuit with buried channel MOSFETs
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T04%3A34%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20gigabit%20MOS%20logic%20circuit%20with%20buried%20channel%20MOSFETs&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Nishiuchi,%20K.&rft.date=1980-10-01&rft.volume=15&rft.issue=5&rft.spage=809&rft.epage=816&rft.pages=809-816&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.1980.1051475&rft_dat=%3Cproquest_RIE%3E28889040%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=23729360&rft_id=info:pmid/&rft_ieee_id=1051475&rfr_iscdi=true