Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM
Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the f...
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| Veröffentlicht in: | IEEE journal on emerging and selected topics in circuits and systems 2016-09, Vol.6 (3), p.364-372 |
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| container_title | IEEE journal on emerging and selected topics in circuits and systems |
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| creator | Nomura, Takao Mori, Ryo Takayanagi, Koji Fukuoka, Kazuki Nii, Koji |
| description | Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce V min degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3. |
| doi_str_mv | 10.1109/JETCAS.2016.2547719 |
| format | Article |
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| source | IEEE/IET Electronic Library |
| subjects | Capacitance Delays Electronics industry Electrostatic discharges Fully digital noise monitor impedance optimization Monitoring pre-bonding test Random access memory simultaneous switching noise Stacking Switches thermal aware memory control through silicon via (TSV) wide I/O DRAM |
| title | Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM |
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