Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects...

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Veröffentlicht in:	IEEE journal of the Electron Devices Society 2021, Vol.9, p.229-235
Hauptverfasser:	Zhou, Longda, Liu, Qianqian, Yang, Hong, Ji, Zhigang, Xu, Hao, Wang, Guilei, Simoen, Eddy, Jiang, Haojie, Luo, Ying, Kong, Zhenzhen, Bai, Guobin, Luo, Jun, Yin, Huaxiang, Zhao, Chao, Wang, Wenwu
Format:	Artikel
Sprache:	eng
Schlagworte:	ALD W gate-filling metal Annealing Atomic layer epitaxy Atomic properties Bias Energy distribution Field effect transistors Logic gates Metallizing Metals negative-bias temperature instability (NBTI) Optimization post-metallization annealing Reduction (metal working) Reliability Semiconductor device measurement Semiconductor devices Si p-FinFETs Tensile stress Thermal variables control Threshold voltage Tin trap generation Tungsten
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