Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on v...

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Veröffentlicht in:	IEEE journal of the Electron Devices Society 2018-01, Vol.6, p.1007-1018
Hauptverfasser:	Beckers, Arnout, Jazaeri, Farzan, Enz, Christian
Format:	Artikel
Sprache:	eng
Schlagworte:	28 nm bulk CMOS 4.2 K CMOS CMOS technology cryo-CMOS cryoelectronics cryogenic Cryogenic engineering Cryogenic temperature Cryogenics Degradation Depletion Field effect transistors freeze-out Integrated circuit modeling interface charge traps Modelling MOS devices MOS transistor modeling Semiconductor device modeling Semiconductor devices slope factor subthreshold swing Temperature Temperature dependence Thickness
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