A network processor architecture for very high speed line interfaces
A network processor architecture that can be used for very high speed line interfaces of carrier-class backbone routers and switches has been developed. The architecture is based on large-scale on-chip multi-processing using static resource scheduling to meet the requirements so that multi-processin...
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| Veröffentlicht in: | Journal of communications and networks 2001-03, Vol.3 (1), p.88-95 |
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| container_end_page | 95 |
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| container_title | Journal of communications and networks |
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| creator | Shimonishi, Hideyuki Murase, Tutomu |
| description | A network processor architecture that can be used for very high speed line interfaces of carrier-class backbone routers and switches has been developed. The architecture is based on large-scale on-chip multi-processing using static resource scheduling to meet the requirements so that multi-processing works efficiently in packet forwarding. Since advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism as well as flexible header handling. The architecture sevaluated by using a prototype hardware design and two typical application examples: IP packet forwarding and ATM/IP multi-layer switching with per-VC/per-flow queuing mechanism. These evaluations show that the architecture can provide various advanced functions for 2.4 Gbps line interfaces even in a common 0.25 m standard cell based LSI design. It can also provide 10 Gbps packet forwarding for basic IP packet handling. |
| doi_str_mv | 10.1109/JCN.2001.6596880 |
| format | Article |
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| ispartof | Journal of communications and networks, 2001-03, Vol.3 (1), p.88-95 |
| issn | 1229-2370 1976-5541 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | backbone Bridges Clocks Computer architecture Hardware high-speed IP networks multi-processor Network processor Pipeline processing QoS Registers |
| title | A network processor architecture for very high speed line interfaces |
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