Bipolar transistor with self-aligned lateral profile
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter s...
Gespeichert in:
| Veröffentlicht in: | IEEE electron device letters 1987-08, Vol.8 (8), p.338-340 |
|---|---|
| Hauptverfasser: | , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 340 |
|---|---|
| container_issue | 8 |
| container_start_page | 338 |
| container_title | IEEE electron device letters |
| container_volume | 8 |
| creator | Li, G.P. Tze-Chiang Chen Ching-Te Chuang Stork, J.M.C. Tang, D.D. Ketchen, M.B. Li-Kong Wang |
| description | This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. |
| doi_str_mv | 10.1109/EDL.1987.26652 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_crossref_primary_10_1109_EDL_1987_26652</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1487202</ieee_id><sourcerecordid>28193930</sourcerecordid><originalsourceid>FETCH-LOGICAL-c379t-5b46816a2b2c6ef1ae484c4a80711b8abe24b71a5d38ef5c6ab87c1a08e1a4a03</originalsourceid><addsrcrecordid>eNqNkL1PwzAQRy0EEqWwsrBkQGwJvtiOnRFK-ZAqscBsXdwLGLlNsVMh_ntSWsHa6ZZ37yc9xs6BFwC8vp7ezQqojS7KqlLlARuBUibnqhKHbMS1hFwAr47ZSUofnIOUWo6YvPWrLmDM-ojL5FPfxezL9-9ZotDmGPzbkuZZwJ4ihmwVu9YHOmVHLYZEZ7s7Zq_305fJYz57fnia3MxyJ3Td56qRlYEKy6Z0FbWAJI10Eg3XAI3BhkrZaEA1F4Za5SpsjHaA3BCgRC7G7GrrHXY_15R6u_DJUQi4pG6dbGmMASnEHiDUohZ7GKXQJVd6AIst6GKXUqTWrqJfYPy2wO0mtx1y201u-5t7eLjcmTE5DO2Q0_n096U1CCM33ost5ono3ynNMFuKH5_9hzs</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>24372057</pqid></control><display><type>article</type><title>Bipolar transistor with self-aligned lateral profile</title><source>IEEE Electronic Library (IEL)</source><creator>Li, G.P. ; Tze-Chiang Chen ; Ching-Te Chuang ; Stork, J.M.C. ; Tang, D.D. ; Ketchen, M.B. ; Li-Kong Wang</creator><creatorcontrib>Li, G.P. ; Tze-Chiang Chen ; Ching-Te Chuang ; Stork, J.M.C. ; Tang, D.D. ; Ketchen, M.B. ; Li-Kong Wang</creatorcontrib><description>This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/EDL.1987.26652</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Bipolar transistors ; Boron ; Circuits ; CMOS process ; Contact resistance ; Electronics ; Exact sciences and technology ; Implants ; Impurities ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Space technology ; Surface topography ; Thickness control ; Transistors</subject><ispartof>IEEE electron device letters, 1987-08, Vol.8 (8), p.338-340</ispartof><rights>1988 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c379t-5b46816a2b2c6ef1ae484c4a80711b8abe24b71a5d38ef5c6ab87c1a08e1a4a03</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1487202$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1487202$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=7713847$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Li, G.P.</creatorcontrib><creatorcontrib>Tze-Chiang Chen</creatorcontrib><creatorcontrib>Ching-Te Chuang</creatorcontrib><creatorcontrib>Stork, J.M.C.</creatorcontrib><creatorcontrib>Tang, D.D.</creatorcontrib><creatorcontrib>Ketchen, M.B.</creatorcontrib><creatorcontrib>Li-Kong Wang</creatorcontrib><title>Bipolar transistor with self-aligned lateral profile</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.</description><subject>Applied sciences</subject><subject>Bipolar transistors</subject><subject>Boron</subject><subject>Circuits</subject><subject>CMOS process</subject><subject>Contact resistance</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Implants</subject><subject>Impurities</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Space technology</subject><subject>Surface topography</subject><subject>Thickness control</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1987</creationdate><recordtype>article</recordtype><recordid>eNqNkL1PwzAQRy0EEqWwsrBkQGwJvtiOnRFK-ZAqscBsXdwLGLlNsVMh_ntSWsHa6ZZ37yc9xs6BFwC8vp7ezQqojS7KqlLlARuBUibnqhKHbMS1hFwAr47ZSUofnIOUWo6YvPWrLmDM-ojL5FPfxezL9-9ZotDmGPzbkuZZwJ4ihmwVu9YHOmVHLYZEZ7s7Zq_305fJYz57fnia3MxyJ3Td56qRlYEKy6Z0FbWAJI10Eg3XAI3BhkrZaEA1F4Za5SpsjHaA3BCgRC7G7GrrHXY_15R6u_DJUQi4pG6dbGmMASnEHiDUohZ7GKXQJVd6AIst6GKXUqTWrqJfYPy2wO0mtx1y201u-5t7eLjcmTE5DO2Q0_n096U1CCM33ost5ono3ynNMFuKH5_9hzs</recordid><startdate>19870801</startdate><enddate>19870801</enddate><creator>Li, G.P.</creator><creator>Tze-Chiang Chen</creator><creator>Ching-Te Chuang</creator><creator>Stork, J.M.C.</creator><creator>Tang, D.D.</creator><creator>Ketchen, M.B.</creator><creator>Li-Kong Wang</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19870801</creationdate><title>Bipolar transistor with self-aligned lateral profile</title><author>Li, G.P. ; Tze-Chiang Chen ; Ching-Te Chuang ; Stork, J.M.C. ; Tang, D.D. ; Ketchen, M.B. ; Li-Kong Wang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c379t-5b46816a2b2c6ef1ae484c4a80711b8abe24b71a5d38ef5c6ab87c1a08e1a4a03</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1987</creationdate><topic>Applied sciences</topic><topic>Bipolar transistors</topic><topic>Boron</topic><topic>Circuits</topic><topic>CMOS process</topic><topic>Contact resistance</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Implants</topic><topic>Impurities</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Space technology</topic><topic>Surface topography</topic><topic>Thickness control</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Li, G.P.</creatorcontrib><creatorcontrib>Tze-Chiang Chen</creatorcontrib><creatorcontrib>Ching-Te Chuang</creatorcontrib><creatorcontrib>Stork, J.M.C.</creatorcontrib><creatorcontrib>Tang, D.D.</creatorcontrib><creatorcontrib>Ketchen, M.B.</creatorcontrib><creatorcontrib>Li-Kong Wang</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, G.P.</au><au>Tze-Chiang Chen</au><au>Ching-Te Chuang</au><au>Stork, J.M.C.</au><au>Tang, D.D.</au><au>Ketchen, M.B.</au><au>Li-Kong Wang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Bipolar transistor with self-aligned lateral profile</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>1987-08-01</date><risdate>1987</risdate><volume>8</volume><issue>8</issue><spage>338</spage><epage>340</epage><pages>338-340</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/EDL.1987.26652</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 1987-08, Vol.8 (8), p.338-340 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_EDL_1987_26652 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Bipolar transistors Boron Circuits CMOS process Contact resistance Electronics Exact sciences and technology Implants Impurities Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Space technology Surface topography Thickness control Transistors |
| title | Bipolar transistor with self-aligned lateral profile |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T03%3A14%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Bipolar%20transistor%20with%20self-aligned%20lateral%20profile&rft.jtitle=IEEE%20electron%20device%20letters&rft.au=Li,%20G.P.&rft.date=1987-08-01&rft.volume=8&rft.issue=8&rft.spage=338&rft.epage=340&rft.pages=338-340&rft.issn=0741-3106&rft.eissn=1558-0563&rft.coden=EDLEDZ&rft_id=info:doi/10.1109/EDL.1987.26652&rft_dat=%3Cproquest_RIE%3E28193930%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=24372057&rft_id=info:pmid/&rft_ieee_id=1487202&rfr_iscdi=true |