Efficient Design of Read Voltages and LDPC codes in NAND Flash Memory using Density Evolution
Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of ma...
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| creator | DUANGTHONGi, C. Phakphisut, W. Wardkein, P. |
| description | Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of maximum likelihood decoding. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory. |
| doi_str_mv | 10.1109/ACCESS.2023.3296250 |
| format | Article |
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Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of maximum likelihood decoding. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.</description><identifier>ISSN: 2169-3536</identifier><identifier>EISSN: 2169-3536</identifier><identifier>DOI: 10.1109/ACCESS.2023.3296250</identifier><identifier>CODEN: IAECCG</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Channel models ; Codes ; Decoding ; density evolution ; Density functional theory ; Design ; Error correcting codes ; Error correction ; Evolutionary algorithms ; Flash memories ; Flash memory (computers) ; LDPC codes ; Low density parity check codes ; Maximum likelihood decoding ; NAND flash memory ; Parity check codes ; read voltages ; Symbols ; Threshold voltage</subject><ispartof>IEEE access, 2023-01, Vol.11, p.1-1</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of maximum likelihood decoding. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.</description><subject>Channel models</subject><subject>Codes</subject><subject>Decoding</subject><subject>density evolution</subject><subject>Density functional theory</subject><subject>Design</subject><subject>Error correcting codes</subject><subject>Error correction</subject><subject>Evolutionary algorithms</subject><subject>Flash memories</subject><subject>Flash memory (computers)</subject><subject>LDPC codes</subject><subject>Low density parity check codes</subject><subject>Maximum likelihood decoding</subject><subject>NAND flash memory</subject><subject>Parity check codes</subject><subject>read voltages</subject><subject>Symbols</subject><subject>Threshold voltage</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNUdtKAzEQXUTBov0CfQj43JrrNnks23qBesGqbxLSzWxN2W402Qr9e1O3SOdlZg5zzgxzsuyC4CEhWF2Pi2I6nw8ppmzIqMqpwEdZj5JcDZhg-fFBfZr1Y1zhFDJBYtTLPqZV5UoHTYsmEN2yQb5CL2Asevd1a5YQkWksmk2eC1R6m1rXoMfx4wTd1CZ-ogdY-7BFm-iaZVJoomu3aPrj603rfHOenVSmjtDf57Ps7Wb6WtwNZk-398V4NiiZUO2AYgBSqlyMFgtGpDUSqCE5FoTLEU4gZ5bnVS5AckIxL41QUhGomGU5t4KdZfedrvVmpb-CW5uw1d44_Qf4sNQmtK6sQUuzEAsQmFIiuB1hWSlrheIcG26woEnrqtP6Cv57A7HVK78JTTpfU8l3r2SMpCnWTZXBxxig-t9KsN7Zojtb9M4WvbclsS47lgOAAwaRAhPFfgFutoXP</recordid><startdate>20230101</startdate><enddate>20230101</enddate><creator>DUANGTHONGi, C.</creator><creator>Phakphisut, W.</creator><creator>Wardkein, P.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain the precise soft information to achieve the performance of maximum likelihood decoding. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. 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| subjects | Channel models Codes Decoding density evolution Density functional theory Design Error correcting codes Error correction Evolutionary algorithms Flash memories Flash memory (computers) LDPC codes Low density parity check codes Maximum likelihood decoding NAND flash memory Parity check codes read voltages Symbols Threshold voltage |
| title | Efficient Design of Read Voltages and LDPC codes in NAND Flash Memory using Density Evolution |
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