Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over bina...

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Veröffentlicht in:	IEEE access 2023-01, Vol.11, p.1-1
Hauptverfasser:	Taherimonfared, Asma, Ciriani, Valentina, Mikkonen, Tommi, Haghparast, Majid
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit design Circuit Optimization Circuit synthesis Costs Demultiplexer Demultiplexers Digital systems Galois fields Garbage Gates (circuits) Logic gates Multiplexer Multiplexing Optimization Power consumption Power management Quantum computing Quaternary Reversible Logic Scalable Realization Transforms
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