Long-Range Pulse Interactions in Unclocked FPGAs
Evidence of long-range interactions between logic transitions in unclocked FPGA circuits is reported. The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction...
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| Veröffentlicht in: | IEEE access 2023-01, Vol.11, p.1-1 |
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| creator | Cohen, Seth D. Fendley, Casey M. Beal, Aubrey N. Corron, Ned J. |
| description | Evidence of long-range interactions between logic transitions in unclocked FPGA circuits is reported. The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays. |
| doi_str_mv | 10.1109/ACCESS.2023.3269433 |
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The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. 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The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays.</description><subject>Asynchronous circuits</subject><subject>Couplings</subject><subject>Delays</subject><subject>feedback circuits</subject><subject>Feedback loop</subject><subject>Feedback loops</subject><subject>Field programmable gate arrays</subject><subject>Lookup tables</subject><subject>network dynamics</subject><subject>non-blocking delay lines</subject><subject>oscillators</subject><subject>pulse circuits</subject><subject>pulse interactions</subject><subject>Steady-state</subject><subject>Table lookup</subject><subject>Transient analysis</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNkEFrAjEQhUNpoWL9Be1hoee1SSbJJkcRtYJQqfUcsklW1tqNza6H_vvGrhTnMsPw3jfDQ-iR4DEhWL1MptPZZjOmmMIYqFAM4AYNKBEqBw7i9mq-R6O23eNUMq14MUB4FZpd_m6anc_Wp0Prs2XT-WhsV4emzeom2zb2EOynd9l8vZi0D-iuMkk3uvQh2s5nH9PXfPW2WE4nq9wCV11uleGcVbhghFaUCscwCKk4sKKkjApiHShXMWcrVwpMS65YRQuimOLYAIYhWvZcF8xeH2P9ZeKPDqbWf4sQd9rErrYHr42gQKEAUbKEdk4BkZxQTIizHluZWM896xjD98m3nd6HU2zS-5pKLCUIzFRSQa-yMbRt9NX_VYL1OWndJ63PSetL0sn11Ltq7_2Vg-ACpIBfnx11Yg</recordid><startdate>20230101</startdate><enddate>20230101</enddate><creator>Cohen, Seth D.</creator><creator>Fendley, Casey M.</creator><creator>Beal, Aubrey N.</creator><creator>Corron, Ned J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The relative positions of pulses traveling in digital feedback loops are observed to dynamically interact and move to equal spacing over long timescales. We confirm the presence of this interaction over different FPGA supply voltages and hypothesize the pulse interactions are due to current draw in the power distribution network of the FPGA. This pulse interaction effect is observed for different FPGA families and manufacturers, including Altera and Xilinx, and has been tested using both look-up table (LUT) and carry chain (CC) logic to realize the feedback delays.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/ACCESS.2023.3269433</doi><tpages>1</tpages><orcidid>https://orcid.org/0000-0001-8313-4941</orcidid><orcidid>https://orcid.org/0000-0001-9782-3799</orcidid><oa>free_for_read</oa></addata></record> |
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| source | IEEE Open Access Journals; DOAJ Directory of Open Access Journals; Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| subjects | Asynchronous circuits Couplings Delays feedback circuits Feedback loop Feedback loops Field programmable gate arrays Lookup tables network dynamics non-blocking delay lines oscillators pulse circuits pulse interactions Steady-state Table lookup Transient analysis |
| title | Long-Range Pulse Interactions in Unclocked FPGAs |
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