NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)
We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory...
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description | We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively. |
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The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively.</description><identifier>ISSN: 2169-3536</identifier><identifier>EISSN: 2169-3536</identifier><identifier>DOI: 10.1109/ACCESS.2020.3004045</identifier><identifier>CODEN: IAECCG</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>Biological neural networks ; Computer architecture ; deep neural network ; Density ; Flash memories ; Flash memory (computers) ; hardware neural network ; in-memory computing ; Inference ; Mathematical analysis ; Matrix algebra ; Matrix methods ; Measurement ; Memory devices ; Multiplication ; NAND flash ; Neural networks ; neuromorphic ; Neuromorphics ; Neurons ; Power consumption ; quantized neural networks ; Random access memory ; Resistance ; Robustness ; Sense amplifiers ; Synapses ; synaptic device ; Training ; Variance ; Virtual machine monitors ; Weight</subject><ispartof>IEEE access, 2020, Vol.8, p.114330-114339</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c408t-9286a7b0499f90061d97b0858149ba81355fc978b97bd28be1c7d4b7955efce23</citedby><cites>FETCH-LOGICAL-c408t-9286a7b0499f90061d97b0858149ba81355fc978b97bd28be1c7d4b7955efce23</cites><orcidid>0000-0003-3559-9802</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9121948$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,777,781,861,2096,4010,27614,27904,27905,27906,54914</link.rule.ids></links><search><creatorcontrib>Lee, Sung-Tae</creatorcontrib><creatorcontrib>Kwon, Dongseok</creatorcontrib><creatorcontrib>Kim, Hyeongsu</creatorcontrib><creatorcontrib>Yoo, Honam</creatorcontrib><creatorcontrib>Lee, Jong-Ho</creatorcontrib><title>NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)</title><title>IEEE access</title><addtitle>Access</addtitle><description>We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively.</description><subject>Biological neural networks</subject><subject>Computer architecture</subject><subject>deep neural network</subject><subject>Density</subject><subject>Flash memories</subject><subject>Flash memory (computers)</subject><subject>hardware neural network</subject><subject>in-memory computing</subject><subject>Inference</subject><subject>Mathematical analysis</subject><subject>Matrix algebra</subject><subject>Matrix methods</subject><subject>Measurement</subject><subject>Memory devices</subject><subject>Multiplication</subject><subject>NAND flash</subject><subject>Neural networks</subject><subject>neuromorphic</subject><subject>Neuromorphics</subject><subject>Neurons</subject><subject>Power consumption</subject><subject>quantized neural networks</subject><subject>Random access memory</subject><subject>Resistance</subject><subject>Robustness</subject><subject>Sense amplifiers</subject><subject>Synapses</subject><subject>synaptic device</subject><subject>Training</subject><subject>Variance</subject><subject>Virtual machine monitors</subject><subject>Weight</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNUcFu1DAUjBBIVKVf0IslLiCRxXbsxD6GbUsrVYtgQRwtO3nuegnxYjtF27_oH-PdVBW-vPfGnpknT1GcE7wgBMuP7XJ5uV4vKKZ4UWHMMOMvihNKallWvKpf_te_Ls5i3OJ8RIZ4c1I8rtrVBboadNygTzpCj1b-Hga03o96l1yH2tBtXIIuTQGQ9QFdu7vNsEffvJliQnrsj0h5AWN0aY--TnpM7uEgBFPQQy7prw-_IvrpUvZwow77450fUdsld6-Ty6236B35gPD7N8Urq4cIZ0_1tPhxdfl9eV3efvl8s2xvy45hkUpJRa0bg5mUVmJck17mSXBBmDRakIpz28lGmAz3VBggXdMz00jOwXZAq9PiZtbtvd6qXXC_82LKa6eOgA93Sof8AwMooQntK0YbaznD0gjSGENwDwy0YYZkrbez1i74PxPEpLZ-CmNeX1HGWU1qIQ6O1fyqCz7GAPbZlWB1iFLNUapDlOopysw6n1kOAJ4ZklAimaj-AfMimRs</recordid><startdate>2020</startdate><enddate>2020</enddate><creator>Lee, Sung-Tae</creator><creator>Kwon, Dongseok</creator><creator>Kim, Hyeongsu</creator><creator>Yoo, Honam</creator><creator>Lee, Jong-Ho</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively.</abstract><cop>Piscataway</cop><pub>IEEE</pub><doi>10.1109/ACCESS.2020.3004045</doi><tpages>10</tpages><orcidid>https://orcid.org/0000-0003-3559-9802</orcidid><oa>free_for_read</oa></addata></record> |
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subjects | Biological neural networks Computer architecture deep neural network Density Flash memories Flash memory (computers) hardware neural network in-memory computing Inference Mathematical analysis Matrix algebra Matrix methods Measurement Memory devices Multiplication NAND flash Neural networks neuromorphic Neuromorphics Neurons Power consumption quantized neural networks Random access memory Resistance Robustness Sense amplifiers Synapses synaptic device Training Variance Virtual machine monitors Weight |
title | NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0) |
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