800 MB/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology

A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm 2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip provides an external 1.2 V unidirectional byte-wi...

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Veröffentlicht in:	IEEE access 2013, Vol.1, p.811-816
Hauptverfasser:	Gillingham, Peter, Chinn, David, Choi, Eric, Jin-Ki Kim, Macdonald, Don, Hakjune Oh, Hong-Beom Pyeon, Schuetz, Roland
Format:	Artikel
Sprache:	eng
Schlagworte:	Concurrent processing Data transfer (computers) Disk drives Flash memeory Flash memory (computers) High-speed integrated circuits Integrated circuits Nonvolatile memory Phase locked loops Rings (mathematics) Shutdowns Topology
Online-Zugang:	Volltext
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