A CMOS programmable analog memory-cell array using floating-gate circuits
The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this p...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2001-01, Vol.48 (1), p.4-11 |
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| container_title | IEEE transactions on circuits and systems. 2, Analog and digital signal processing |
| container_volume | 48 |
| creator | Harrison, R.R. Bragg, J.A. Hasler, P. Minch, B.A. Deweerth, S.P. |
| description | The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells. |
| doi_str_mv | 10.1109/82.913181 |
| format | Article |
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Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.</description><identifier>ISSN: 1057-7130</identifier><identifier>EISSN: 1558-125X</identifier><identifier>DOI: 10.1109/82.913181</identifier><identifier>CODEN: ICSPE5</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CMOS analog integrated circuits ; CMOS memory circuits ; Maintenance engineering ; Neuromorphics ; Nonvolatile memory ; Pins ; Potentiometers ; Power engineering and energy ; Very large scale integration ; Voltage</subject><ispartof>IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-01, Vol.48 (1), p.4-11</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2001</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c304t-e3de61c10424c388609a889c322d1ed6554634e3a11c266d6a6648dd349aaef53</citedby><cites>FETCH-LOGICAL-c304t-e3de61c10424c388609a889c322d1ed6554634e3a11c266d6a6648dd349aaef53</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/913181$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/913181$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Harrison, R.R.</creatorcontrib><creatorcontrib>Bragg, J.A.</creatorcontrib><creatorcontrib>Hasler, P.</creatorcontrib><creatorcontrib>Minch, B.A.</creatorcontrib><creatorcontrib>Deweerth, S.P.</creatorcontrib><title>A CMOS programmable analog memory-cell array using floating-gate circuits</title><title>IEEE transactions on circuits and systems. 2, Analog and digital signal processing</title><addtitle>T-CAS2</addtitle><description>The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. 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With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells.</description><subject>CMOS analog integrated circuits</subject><subject>CMOS memory circuits</subject><subject>Maintenance engineering</subject><subject>Neuromorphics</subject><subject>Nonvolatile memory</subject><subject>Pins</subject><subject>Potentiometers</subject><subject>Power engineering and energy</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>1057-7130</issn><issn>1558-125X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkL1PwzAQxSMEEqUwsDJZDEgMKT7bcZ2xqvioVNQBkNisw7lEqZKm2MnQ_x5XQQxM96T73em9lyTXwGcAPH8wYpaDBAMnyQSyzKQgss_TqHk2T-cg-XlyEcKWc24gN5NktWDL180b2_uu8ti2-NUQwx02XcVaajt_SB01DUPv8cCGUO8qVjYd9lGkFfbEXO3dUPfhMjkrsQl09TunycfT4_vyJV1vnlfLxTp1kqs-JVmQBgdcCeWkMZrnaEzupBAFUKGzTGmpSCKAE1oXGrVWpiikyhGpzOQ0uRv_RsvfA4XetnU4esQddUOw8UhrEPMI3v4Dt93gY7RgjVFazDnPI3Q_Qs53IXgq7d7XLfqDBW6PjVoj7NhoZG9GtiaiP-53-QO1zW7q</recordid><startdate>200101</startdate><enddate>200101</enddate><creator>Harrison, R.R.</creator><creator>Bragg, J.A.</creator><creator>Hasler, P.</creator><creator>Minch, B.A.</creator><creator>Deweerth, S.P.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| ispartof | IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-01, Vol.48 (1), p.4-11 |
| issn | 1057-7130 1558-125X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | CMOS analog integrated circuits CMOS memory circuits Maintenance engineering Neuromorphics Nonvolatile memory Pins Potentiometers Power engineering and energy Very large scale integration Voltage |
| title | A CMOS programmable analog memory-cell array using floating-gate circuits |
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