An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances
We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (4...
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| Veröffentlicht in: | IEEE transactions on applied superconductivity 1997-06, Vol.7 (2), p.2638-2643 |
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| container_end_page | 2643 |
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| container_issue | 2 |
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| container_title | IEEE transactions on applied superconductivity |
| container_volume | 7 |
| creator | Kerber, G.L. Abelson, L.A. Elmadjian, R.N. Hanaya, G. Ladizinsky, E.G. |
| description | We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process. |
| doi_str_mv | 10.1109/77.621781 |
| format | Article |
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The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.</description><identifier>ISSN: 1051-8223</identifier><identifier>EISSN: 1558-2515</identifier><identifier>DOI: 10.1109/77.621781</identifier><identifier>CODEN: ITASE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Atomic force microscopy ; Atomic layer deposition ; Atomic measurements ; Dielectric substrates ; Electronics ; Exact sciences and technology ; Force measurement ; Frequency measurement ; Integrated circuit technology ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Sputtering ; Superconducting devices ; Superconducting integrated circuits ; Superconductivity</subject><ispartof>IEEE transactions on applied superconductivity, 1997-06, Vol.7 (2), p.2638-2643</ispartof><rights>1997 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c403t-d1386dcaf8ee38a2a1ac4e71ac3167511946a9950892c023f1ee0ac31a96971c3</citedby><cites>FETCH-LOGICAL-c403t-d1386dcaf8ee38a2a1ac4e71ac3167511946a9950892c023f1ee0ac31a96971c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/621781$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/621781$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=2809214$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kerber, G.L.</creatorcontrib><creatorcontrib>Abelson, L.A.</creatorcontrib><creatorcontrib>Elmadjian, R.N.</creatorcontrib><creatorcontrib>Hanaya, G.</creatorcontrib><creatorcontrib>Ladizinsky, E.G.</creatorcontrib><title>An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances</title><title>IEEE transactions on applied superconductivity</title><addtitle>TASC</addtitle><description>We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.</description><subject>Applied sciences</subject><subject>Atomic force microscopy</subject><subject>Atomic layer deposition</subject><subject>Atomic measurements</subject><subject>Dielectric substrates</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Force measurement</subject><subject>Frequency measurement</subject><subject>Integrated circuit technology</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Sputtering</subject><subject>Superconducting devices</subject><subject>Superconducting integrated circuits</subject><subject>Superconductivity</subject><issn>1051-8223</issn><issn>1558-2515</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><recordid>eNqNkD1PwzAQhiMEElAYWJk8ICSGgM-JY2esKr4kBAvM0eFciiFNiu2A-Pc4pOrMYp_1Pn7suyQ5AX4JwMsrpS4LAUrDTnIAUupUSJC7seYSUi1Etp8cev_OOeQ6lweJn3fMrtau_6KaPb4-MtsFWjoM8WisM4MNLKaGvGcNYRic7ZYsvFnz8YcvXT90NVu32BHDWLX9Nzm2RofeBmu2EtvVgwnYRdNRstdg6-l4s8-Sl5vr58Vd-vB0e7-YP6Qm51lIa8h0URtsNFGmUSCgyUnFNYNCSYAyL7AsJdelMFxkDRDxMcSyKBWYbJacT97YwOdAPlQr6w2141_7wVdCKynj0P4B5uOLeQQvJtC43ntHTbV2doXupwJejfOvlKqm-Uf2bCNFb7BtXOzd-u0FoXkpYFSeTpglom26cfwCo2eNrw</recordid><startdate>19970601</startdate><enddate>19970601</enddate><creator>Kerber, G.L.</creator><creator>Abelson, L.A.</creator><creator>Elmadjian, R.N.</creator><creator>Hanaya, G.</creator><creator>Ladizinsky, E.G.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>7QQ</scope><scope>JG9</scope></search><sort><creationdate>19970601</creationdate><title>An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances</title><author>Kerber, G.L. ; Abelson, L.A. ; Elmadjian, R.N. ; Hanaya, G. ; Ladizinsky, E.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c403t-d1386dcaf8ee38a2a1ac4e71ac3167511946a9950892c023f1ee0ac31a96971c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Applied sciences</topic><topic>Atomic force microscopy</topic><topic>Atomic layer deposition</topic><topic>Atomic measurements</topic><topic>Dielectric substrates</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Force measurement</topic><topic>Frequency measurement</topic><topic>Integrated circuit technology</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Sputtering</topic><topic>Superconducting devices</topic><topic>Superconducting integrated circuits</topic><topic>Superconductivity</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kerber, G.L.</creatorcontrib><creatorcontrib>Abelson, L.A.</creatorcontrib><creatorcontrib>Elmadjian, R.N.</creatorcontrib><creatorcontrib>Hanaya, G.</creatorcontrib><creatorcontrib>Ladizinsky, E.G.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Ceramic Abstracts</collection><collection>Materials Research Database</collection><jtitle>IEEE transactions on applied superconductivity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kerber, G.L.</au><au>Abelson, L.A.</au><au>Elmadjian, R.N.</au><au>Hanaya, G.</au><au>Ladizinsky, E.G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>1997-06-01</date><risdate>1997</risdate><volume>7</volume><issue>2</issue><spage>2638</spage><epage>2643</epage><pages>2638-2643</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/77.621781</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE transactions on applied superconductivity, 1997-06, Vol.7 (2), p.2638-2643 |
| issn | 1051-8223 1558-2515 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Atomic force microscopy Atomic layer deposition Atomic measurements Dielectric substrates Electronics Exact sciences and technology Force measurement Frequency measurement Integrated circuit technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sputtering Superconducting devices Superconducting integrated circuits Superconductivity |
| title | An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances |
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