Superconductive multi-chip module process for high speed digital applications
We report on the development of a superconducting multi-chip module (MCM) process for high speed digital packaging applications, which allows superconducting microstrip connections of superconducting chips with impedances up to 50 /spl Omega/. The MCM process uses a low temperature polymer, benzocyc...
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| Veröffentlicht in: | IEEE transactions on applied superconductivity 1997-06, Vol.7 (2), p.2627-2630 |
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| container_end_page | 2630 |
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| container_title | IEEE transactions on applied superconductivity |
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| creator | Abelson, L.A. Elmadjian, R.N. Kerber, G.L. Smith, A.D. |
| description | We report on the development of a superconducting multi-chip module (MCM) process for high speed digital packaging applications, which allows superconducting microstrip connections of superconducting chips with impedances up to 50 /spl Omega/. The MCM process uses a low temperature polymer, benzocyclobutene (BCB) dielectric, which has excellent planarization properties (>90%). The six mask MCM process uses three Nb wire layers, two BCB layers, and Ti/Pd/Au for the pad metallization. To maximize yield of 32 mm square MCM die, we optimized Nb deposition and BCB curing parameters to minimize stress-induced failures and reduce defect density. Current-carrying capabilities of signal lines and vias (5 /spl mu/m minimum design rule) are in excess of 20 mA//spl mu/m linewidth. We discuss successful packaging of superconducting chips, demonstrating error-free operation up to 5 Gbit/s, and other process improvements, such as the use of NbN wiring for 10 K operation. |
| doi_str_mv | 10.1109/77.621778 |
| format | Article |
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The MCM process uses a low temperature polymer, benzocyclobutene (BCB) dielectric, which has excellent planarization properties (>90%). The six mask MCM process uses three Nb wire layers, two BCB layers, and Ti/Pd/Au for the pad metallization. To maximize yield of 32 mm square MCM die, we optimized Nb deposition and BCB curing parameters to minimize stress-induced failures and reduce defect density. Current-carrying capabilities of signal lines and vias (5 /spl mu/m minimum design rule) are in excess of 20 mA//spl mu/m linewidth. We discuss successful packaging of superconducting chips, demonstrating error-free operation up to 5 Gbit/s, and other process improvements, such as the use of NbN wiring for 10 K operation.</description><identifier>ISSN: 1051-8223</identifier><identifier>EISSN: 1558-2515</identifier><identifier>DOI: 10.1109/77.621778</identifier><identifier>CODEN: ITASE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Dielectrics ; Electronics ; Exact sciences and technology ; Impedance ; Microstrip ; Niobium ; Packaging ; Polymers ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The MCM process uses a low temperature polymer, benzocyclobutene (BCB) dielectric, which has excellent planarization properties (>90%). The six mask MCM process uses three Nb wire layers, two BCB layers, and Ti/Pd/Au for the pad metallization. To maximize yield of 32 mm square MCM die, we optimized Nb deposition and BCB curing parameters to minimize stress-induced failures and reduce defect density. Current-carrying capabilities of signal lines and vias (5 /spl mu/m minimum design rule) are in excess of 20 mA//spl mu/m linewidth. We discuss successful packaging of superconducting chips, demonstrating error-free operation up to 5 Gbit/s, and other process improvements, such as the use of NbN wiring for 10 K operation.</description><subject>Applied sciences</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Impedance</subject><subject>Microstrip</subject><subject>Niobium</subject><subject>Packaging</subject><subject>Polymers</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Superconducting devices</subject><subject>Superconducting epitaxial layers</subject><subject>Superconducting filaments and wires</subject><subject>Superconductivity</subject><subject>Temperature</subject><issn>1051-8223</issn><issn>1558-2515</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><recordid>eNqN0U1LxDAQBuAgCq6rB6-eehDBQ9dMsmnToyx-wYoH9VzSZLIbST9MWsF_b6XLXvU0A_PMy8AQcg50AUCLmzxfZAzyXB6QGQghUyZAHI49FZBKxvgxOYnxg1JYyqWYkefXocOg28YMundfmNSD712qt65L6tYMHpMutBpjTGwbkq3bbJPYIZrEuI3rlU9U13mnVe_aJp6SI6t8xLNdnZP3-7u31WO6fnl4Wt2uU80z2aeywNxqWWiFKCSlVBhtuQBrQAFTnEFRVRVkxpgKLdVcCQRuleJAjRjpnFxNueNtnwPGvqxd1Oi9arAdYsmKDLjk8DeUMgOxlP-A2XhgTkd4PUEd2hgD2rILrlbhuwRa_r6gzPNyesFoL3ehKmrlbVCNdnG_wCSVhWQju5iYQ8T9dJfxA7EGjxw</recordid><startdate>19970601</startdate><enddate>19970601</enddate><creator>Abelson, L.A.</creator><creator>Elmadjian, R.N.</creator><creator>Kerber, G.L.</creator><creator>Smith, A.D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>8BQ</scope><scope>JG9</scope><scope>7TB</scope><scope>FR3</scope></search><sort><creationdate>19970601</creationdate><title>Superconductive multi-chip module process for high speed digital applications</title><author>Abelson, L.A. ; Elmadjian, R.N. ; Kerber, G.L. ; Smith, A.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c368t-89e7fc89caee580005dcf351fd1a12a3219bbb16dddbef0c3a5e13faa310d5cf3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Applied sciences</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Impedance</topic><topic>Microstrip</topic><topic>Niobium</topic><topic>Packaging</topic><topic>Polymers</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Superconducting devices</topic><topic>Superconducting epitaxial layers</topic><topic>Superconducting filaments and wires</topic><topic>Superconductivity</topic><topic>Temperature</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Abelson, L.A.</creatorcontrib><creatorcontrib>Elmadjian, R.N.</creatorcontrib><creatorcontrib>Kerber, G.L.</creatorcontrib><creatorcontrib>Smith, A.D.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>METADEX</collection><collection>Materials Research Database</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on applied superconductivity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Abelson, L.A.</au><au>Elmadjian, R.N.</au><au>Kerber, G.L.</au><au>Smith, A.D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Superconductive multi-chip module process for high speed digital applications</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>1997-06-01</date><risdate>1997</risdate><volume>7</volume><issue>2</issue><spage>2627</spage><epage>2630</epage><pages>2627-2630</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>We report on the development of a superconducting multi-chip module (MCM) process for high speed digital packaging applications, which allows superconducting microstrip connections of superconducting chips with impedances up to 50 /spl Omega/. The MCM process uses a low temperature polymer, benzocyclobutene (BCB) dielectric, which has excellent planarization properties (>90%). The six mask MCM process uses three Nb wire layers, two BCB layers, and Ti/Pd/Au for the pad metallization. To maximize yield of 32 mm square MCM die, we optimized Nb deposition and BCB curing parameters to minimize stress-induced failures and reduce defect density. Current-carrying capabilities of signal lines and vias (5 /spl mu/m minimum design rule) are in excess of 20 mA//spl mu/m linewidth. We discuss successful packaging of superconducting chips, demonstrating error-free operation up to 5 Gbit/s, and other process improvements, such as the use of NbN wiring for 10 K operation.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/77.621778</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 1051-8223 |
| ispartof | IEEE transactions on applied superconductivity, 1997-06, Vol.7 (2), p.2627-2630 |
| issn | 1051-8223 1558-2515 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Dielectrics Electronics Exact sciences and technology Impedance Microstrip Niobium Packaging Polymers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Superconducting devices Superconducting epitaxial layers Superconducting filaments and wires Superconductivity Temperature |
| title | Superconductive multi-chip module process for high speed digital applications |
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