A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications
A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage,...
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Veröffentlicht in: | IEEE journal of solid-state circuits 2002-04, Vol.37 (4), p.459-470 |
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container_title | IEEE journal of solid-state circuits |
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creator | Chi-Wa Lo Luong, H.C. |
description | A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset. |
doi_str_mv | 10.1109/4.991384 |
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It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.991384</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Arrays ; Capacitance ; Chips ; CMOS ; CMOS process ; Electric potential ; Energy consumption ; Filters ; Frequency synthesizers ; Low voltage ; Noise ; Phase locked loops ; Phased arrays ; Power supplies ; Switching circuits ; Synthesizers</subject><ispartof>IEEE journal of solid-state circuits, 2002-04, Vol.37 (4), p.459-470</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2002</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-1c880c070ad9b7e7bcb18d15dc4371b2543a56a7f0232c9a7cf9b6e203bd03983</citedby><cites>FETCH-LOGICAL-c365t-1c880c070ad9b7e7bcb18d15dc4371b2543a56a7f0232c9a7cf9b6e203bd03983</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/991384$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/991384$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chi-Wa Lo</creatorcontrib><creatorcontrib>Luong, H.C.</creatorcontrib><title>A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. 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The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.</description><subject>Arrays</subject><subject>Capacitance</subject><subject>Chips</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>Electric potential</subject><subject>Energy consumption</subject><subject>Filters</subject><subject>Frequency synthesizers</subject><subject>Low voltage</subject><subject>Noise</subject><subject>Phase locked loops</subject><subject>Phased arrays</subject><subject>Power supplies</subject><subject>Switching circuits</subject><subject>Synthesizers</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0U1LAzEQBuAgCtYP8OwpeFAvW2c2ySY5lqJWUDz4gSeXbJq1Kdvdmmwp7a93pcWDBz0NwzwMM7yEnCD0EUFf8b7WyBTfIT0UQiUo2dsu6QGgSnQKsE8OYpx2LecKe-R9QLEvkleqAZKH0ZrOmrqpfDvxlg4fHp9oaWKbxKVv7cTXH7QM7nPharuicVW3Exf92gVaNoEufXCVi5Ga-bzy1rS-qeMR2StNFd3xth6Sl5vr5-EouX-8vRsO7hPLMtEmaJUCCxLMWBfSycIWqMYoxpYziUUqODMiM7KElKVWG2lLXWQuBVaMgWnFDsnFZu88NN19sc1nPlpXVaZ2zSLmGqTmqLNvef6nTBVmKFH8DyVwpiDr4NkvOG0Woe7ezbVOleRa6A5dbpANTYzBlfk8-JkJqxwh_w4u5_kmuI6ebqh3zv2w7fALgSCQ4w</recordid><startdate>20020401</startdate><enddate>20020401</enddate><creator>Chi-Wa Lo</creator><creator>Luong, H.C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/4.991384</doi><tpages>12</tpages></addata></record> |
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subjects | Arrays Capacitance Chips CMOS CMOS process Electric potential Energy consumption Filters Frequency synthesizers Low voltage Noise Phase locked loops Phased arrays Power supplies Switching circuits Synthesizers |
title | A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications |
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