A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage,...

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Veröffentlicht in:IEEE journal of solid-state circuits 2002-04, Vol.37 (4), p.459-470
Hauptverfasser: Chi-Wa Lo, Luong, H.C.
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container_title IEEE journal of solid-state circuits
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creator Chi-Wa Lo
Luong, H.C.
description A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-/spl mu/m CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 /spl times/ 1.1 mm/sup 2/. The settling time is less than 100 /spl mu/s and the phase noise is -118 dBc/Hz at 600-kHz offset.
doi_str_mv 10.1109/4.991384
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ispartof IEEE journal of solid-state circuits, 2002-04, Vol.37 (4), p.459-470
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source IEEE Electronic Library (IEL)
subjects Arrays
Capacitance
Chips
CMOS
CMOS process
Electric potential
Energy consumption
Filters
Frequency synthesizers
Low voltage
Noise
Phase locked loops
Phased arrays
Power supplies
Switching circuits
Synthesizers
title A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications
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