A dynamic three-state memory cell for high-density associative processors

A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1991-04, Vol.26 (4), p.537-541
Hauptverfasser:	Herrmann, F.P., Keast, C.L., Ishio, K., Wade, J.P., Sodini, C.G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Associative processing Central Processing Unit Charge coupled devices CMOS technology Electronics Exact sciences and technology MOSFETs Parallel processing Random access memory Read-write memory Student members System performance
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