Low-power SRAM design using half-swing pulse-mode techniques
This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, a...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1998-11, Vol.33 (11), p.1659-1671 |
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| container_end_page | 1671 |
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| container_issue | 11 |
| container_start_page | 1659 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 33 |
| creator | Mai, K.W. Mori, T. Amrutur, B.S. Ho, R. Wilburn, B. Horowitz, M.A. Fukushi, I. Izawa, T. Mitarai, S. |
| description | This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K/spl times/16-b SRAM fabricated in a 0.25-/spl mu/m dual-V/sub t/ CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes. |
| doi_str_mv | 10.1109/4.726555 |
| format | Article |
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These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K/spl times/16-b SRAM fabricated in a 0.25-/spl mu/m dual-V/sub t/ CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.726555</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Circuits ; CMOS technology ; Decoding ; Leakage current ; Power dissipation ; Pulse amplifiers ; Random access memory ; Switches ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1659-1671</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c275t-85bcc6cea33a3bdce74c27f924b3f7492cb142c7f2b29d1b3ba126ad3657a0443</citedby><cites>FETCH-LOGICAL-c275t-85bcc6cea33a3bdce74c27f924b3f7492cb142c7f2b29d1b3ba126ad3657a0443</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/726555$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/726555$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mai, K.W.</creatorcontrib><creatorcontrib>Mori, T.</creatorcontrib><creatorcontrib>Amrutur, B.S.</creatorcontrib><creatorcontrib>Ho, R.</creatorcontrib><creatorcontrib>Wilburn, B.</creatorcontrib><creatorcontrib>Horowitz, M.A.</creatorcontrib><creatorcontrib>Fukushi, I.</creatorcontrib><creatorcontrib>Izawa, T.</creatorcontrib><creatorcontrib>Mitarai, S.</creatorcontrib><title>Low-power SRAM design using half-swing pulse-mode techniques</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. 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On-chip voltage samplers were used to probe internal nodes.</description><subject>Capacitance</subject><subject>Circuits</subject><subject>CMOS technology</subject><subject>Decoding</subject><subject>Leakage current</subject><subject>Power dissipation</subject><subject>Pulse amplifiers</subject><subject>Random access memory</subject><subject>Switches</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMlLxDAYxYMoWEfBs6eexEvGrE0LXobBDSqCC3gLSfp1ptLNpqX439vSwdO3vB_vwUPokpI1pSS5FWvFIinlEQqolDGmin8do4AQGuOEEXKKzrz_nk4hYhqgu7QZcduM0IXvb5uXMANf7Opw8EW9C_emzLEf57UdSg-4ajIIe3D7uvgZwJ-jk9xM_4vDXKHPh_uP7RNOXx-ft5sUO6Zkj2NpnYscGM4Nt5kDJSYhT5iwPFciYc5SwZzKmWVJRi23hrLIZDySyhAh-ApdL75t18y5va4K76AsTQ3N4DWLuWScRRN4s4Cua7zvINdtV1Sm-9WU6LkeLfRSz4ReLWgBAP_YQfwDhulfMw</recordid><startdate>199811</startdate><enddate>199811</enddate><creator>Mai, K.W.</creator><creator>Mori, T.</creator><creator>Amrutur, B.S.</creator><creator>Ho, R.</creator><creator>Wilburn, B.</creator><creator>Horowitz, M.A.</creator><creator>Fukushi, I.</creator><creator>Izawa, T.</creator><creator>Mitarai, S.</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199811</creationdate><title>Low-power SRAM design using half-swing pulse-mode techniques</title><author>Mai, K.W. ; Mori, T. ; Amrutur, B.S. ; Ho, R. ; Wilburn, B. ; Horowitz, M.A. ; Fukushi, I. ; Izawa, T. ; Mitarai, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c275t-85bcc6cea33a3bdce74c27f924b3f7492cb142c7f2b29d1b3ba126ad3657a0443</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Capacitance</topic><topic>Circuits</topic><topic>CMOS technology</topic><topic>Decoding</topic><topic>Leakage current</topic><topic>Power dissipation</topic><topic>Pulse amplifiers</topic><topic>Random access memory</topic><topic>Switches</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mai, K.W.</creatorcontrib><creatorcontrib>Mori, T.</creatorcontrib><creatorcontrib>Amrutur, B.S.</creatorcontrib><creatorcontrib>Ho, R.</creatorcontrib><creatorcontrib>Wilburn, B.</creatorcontrib><creatorcontrib>Horowitz, M.A.</creatorcontrib><creatorcontrib>Fukushi, I.</creatorcontrib><creatorcontrib>Izawa, T.</creatorcontrib><creatorcontrib>Mitarai, S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mai, K.W.</au><au>Mori, T.</au><au>Amrutur, B.S.</au><au>Ho, R.</au><au>Wilburn, B.</au><au>Horowitz, M.A.</au><au>Fukushi, I.</au><au>Izawa, T.</au><au>Mitarai, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Low-power SRAM design using half-swing pulse-mode techniques</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1998-11</date><risdate>1998</risdate><volume>33</volume><issue>11</issue><spage>1659</spage><epage>1671</epage><pages>1659-1671</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K/spl times/16-b SRAM fabricated in a 0.25-/spl mu/m dual-V/sub t/ CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes.</abstract><pub>IEEE</pub><doi>10.1109/4.726555</doi><tpages>13</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1659-1671 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Capacitance Circuits CMOS technology Decoding Leakage current Power dissipation Pulse amplifiers Random access memory Switches Voltage |
| title | Low-power SRAM design using half-swing pulse-mode techniques |
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