Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"
For original paper see J. Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1997-10, Vol.32 (10), p.1610-1611, Article 1610 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 32 |
| creator | Blair, G.M. |
| description | For original paper see J. Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions. |
| doi_str_mv | 10.1109/4.634673 |
| format | Article |
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Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. 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Yuan and C. Svensson, ibid., vol.32, pp.62-69 (1997). In a recent paper, Yuan and Svensson propose various single-clock differential flip-flops; however, those using a dynamic slave are unsafe in the presence of input glitches. Further, a double-edge triggered flip-flop is developed from one of the semistatic versions.</abstract><pub>IEEE</pub><doi>10.1109/4.634673</doi><tpages>2</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Capacitance Circuit synthesis Clocks CMOS logic circuits CMOS technology Flip-flops Latches Master-slave Solid state circuits Switches |
| title | Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings" |
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