2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor

Novel 2.5 V CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and a leakless buffer circuit are applied to a floating point macrocell for a 200 MHz superscalar RISC processor. The NTP circuit has two advantages: high noise immunity and high speed. Floating point operations c...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1996-07, Vol.31 (7), p.972-980
Hauptverfasser:	Murabayashi, F., Yamauchi, T., Yamada, H., Nishiyama, T., Shimamura, K., Tanaka, S., Hotta, T., Shimizu, T., Sawamoto, H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit noise CMOS process CMOS technology Delay Macrocell networks MOS devices Power dissipation Power supplies Reduced instruction set computing Registers
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