A multiplexer-based architecture for high-density, low-power gate arrays
This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to cr...
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Veröffentlicht in: | IEEE journal of solid-state circuits 1995-04, Vol.30 (4), p.392-396 |
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container_title | IEEE journal of solid-state circuits |
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creator | Landers, R.J. Mahant-Shetti, S.S. Lemonds, C. |
description | This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology.< > |
doi_str_mv | 10.1109/4.375958 |
format | Article |
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The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.375958</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit properties ; Degradation ; Delay ; Driver circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Feeds ; Instruments ; Libraries ; Multiplexing ; Power dissipation ; Product design ; SPICE ; Switching, multiplexing, switched capacity circuits</subject><ispartof>IEEE journal of solid-state circuits, 1995-04, Vol.30 (4), p.392-396</ispartof><rights>1995 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c335t-bf65737003f1fffcd1d03883a718e17b196dbdcaa0544b6d3b65e0c02970aa943</citedby><cites>FETCH-LOGICAL-c335t-bf65737003f1fffcd1d03883a718e17b196dbdcaa0544b6d3b65e0c02970aa943</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/375958$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23930,23931,25140,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/375958$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3536934$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Landers, R.J.</creatorcontrib><creatorcontrib>Mahant-Shetti, S.S.</creatorcontrib><creatorcontrib>Lemonds, C.</creatorcontrib><title>A multiplexer-based architecture for high-density, low-power gate arrays</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology.< ></description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Degradation</subject><subject>Delay</subject><subject>Driver circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Feeds</subject><subject>Instruments</subject><subject>Libraries</subject><subject>Multiplexing</subject><subject>Power dissipation</subject><subject>Product design</subject><subject>SPICE</subject><subject>Switching, multiplexing, switched capacity circuits</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1995</creationdate><recordtype>article</recordtype><recordid>eNqN0MFLwzAUBvAgCs4pePbUg4gHM1-apE2OY6gTBl4UvJU0fdki3VqTjrn_3o6KXj09Hu_Hx-Mj5JLBhDHQ92LCc6mlOiIjJqWiLOfvx2QEwBTVKcApOYvxo1-FUGxE5tNkva0739b4hYGWJmKVmGBXvkPbbQMmrgnJyi9XtMJN9N3-LqmbHW2bHYZkaTrsdTD7eE5OnKkjXvzMMXl7fHidzeni5el5Nl1Qy7nsaOkymfMcgDvmnLMVq4ArxU3OFLK8ZDqrysoaA1KIMqt4mUkEC6nOwRgt-JjcDLltaD63GLti7aPFujYbbLaxSJXmQqXwD8g1SzPdw9sB2tDEGNAVbfBrE_YFg-LQaSGKodOeXv9kmmhN7YLZWB9_PZe8zzv8eDUwj4h_1yHjG_01fcE</recordid><startdate>19950401</startdate><enddate>19950401</enddate><creator>Landers, R.J.</creator><creator>Mahant-Shetti, S.S.</creator><creator>Lemonds, C.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19950401</creationdate><title>A multiplexer-based architecture for high-density, low-power gate arrays</title><author>Landers, R.J. ; Mahant-Shetti, S.S. ; Lemonds, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c335t-bf65737003f1fffcd1d03883a718e17b196dbdcaa0544b6d3b65e0c02970aa943</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>Degradation</topic><topic>Delay</topic><topic>Driver circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Feeds</topic><topic>Instruments</topic><topic>Libraries</topic><topic>Multiplexing</topic><topic>Power dissipation</topic><topic>Product design</topic><topic>SPICE</topic><topic>Switching, multiplexing, switched capacity circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Landers, R.J.</creatorcontrib><creatorcontrib>Mahant-Shetti, S.S.</creatorcontrib><creatorcontrib>Lemonds, C.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Landers, R.J.</au><au>Mahant-Shetti, S.S.</au><au>Lemonds, C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A multiplexer-based architecture for high-density, low-power gate arrays</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1995-04-01</date><risdate>1995</risdate><volume>30</volume><issue>4</issue><spage>392</spage><epage>396</epage><pages>392-396</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16/spl times/16-b multiplier operating at 50 MHz in 314500 /spl mu/m/sup 2/ in 0.6 /spl mu/m technology.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.375958</doi><tpages>5</tpages></addata></record> |
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subjects | Applied sciences Circuit properties Degradation Delay Driver circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Feeds Instruments Libraries Multiplexing Power dissipation Product design SPICE Switching, multiplexing, switched capacity circuits |
title | A multiplexer-based architecture for high-density, low-power gate arrays |
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