Simultaneous routing and buffer insertion with restrictions on buffer locations
During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2000-07, Vol.19 (7), p.819-824 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Hai Zhou Wong, D.F. I-Min Liu Aziz, A. |
| description | During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay. |
| doi_str_mv | 10.1109/43.851998 |
| format | Article |
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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2000-07, Vol.19 (7), p.819-824 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_43_851998 |
| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Automata Buffers Circuit synthesis Circuit testing Computer aided design Constrictions Delay Design automation Design engineering Gold Insertion Iterative methods Latches Logic Routing Sequential circuits Wire |
| title | Simultaneous routing and buffer insertion with restrictions on buffer locations |
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