The Gmicro/100 32-bit microprocessor

The Gmicro/100 32-bit microprocessor

A description is given of the Gmicro/100, a 32-b VLSI microprocessor based on the TRON specification. The Gmicro/100 five-stage pipeline, prejump mechanism, and bitmap manipulation are examined. Performance results are reported. They show that the prejump mechanism, implemented as a hardware solutio...

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Veröffentlicht in:IEEE MICRO 1991-08, Vol.11 (4), p.20-23
Hauptverfasser: Yoshida, T., Shimisu, T., Mizugaki, S., Hinata, J.
Format: Artikel
Sprache:eng
Schlagworte:
Adders
Clocks
CMOS process
Counting circuits
Decoding
Microprocessors
Pipeline processing
Prefetching
Read only memory
Transfer functions
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container_end_page 23
container_issue 4
container_start_page 20
container_title IEEE MICRO
container_volume 11
creator Yoshida, T.
Shimisu, T.
Mizugaki, S.
Hinata, J.
description A description is given of the Gmicro/100, a 32-b VLSI microprocessor based on the TRON specification. The Gmicro/100 five-stage pipeline, prejump mechanism, and bitmap manipulation are examined. Performance results are reported. They show that the prejump mechanism, implemented as a hardware solution for the jump problem, executes benchmark programs 16.8% faster on the average. Optimized microinstructions permit bitmap-manipulation instructions to perform two to five times faster than the software loops. The application-specific standard product approach used to implement Gmicro/100 is discussed.< >
doi_str_mv 10.1109/40.85722
format Article
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source IEEE Electronic Library (IEL)
subjects Adders
Clocks
CMOS process
Counting circuits
Decoding
Microprocessors
Pipeline processing
Prefetching
Read only memory
Transfer functions
title The Gmicro/100 32-bit microprocessor
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