A universal nonlinear component and its application to WSI
Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every...
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Veröffentlicht in: | IEEE transactions on components, hybrids, and manufacturing technology hybrids, and manufacturing technology, 1993-11, Vol.16 (7), p.656-664 |
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creator | Jain, V.K. Wadekar, S.A. Lei Lin |
description | Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology.< > |
doi_str_mv | 10.1109/33.257869 |
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Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology.< ></description><identifier>ISSN: 0148-6411</identifier><identifier>EISSN: 1558-3082</identifier><identifier>DOI: 10.1109/33.257869</identifier><identifier>CODEN: ITTEDR</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Clocks ; CMOS technology ; Coprocessors ; Design. Technologies. Operation analysis. Testing ; Digital signal processing chips ; Electronics ; Exact sciences and technology ; Image processing ; Integrated circuits ; Interpolation ; Read only memory ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal processing ; Signal processing algorithms ; Wafer scale integration</subject><ispartof>IEEE transactions on components, hybrids, and manufacturing technology, 1993-11, Vol.16 (7), p.656-664</ispartof><rights>1994 INIST-CNRS</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c372t-1be06619cd1b815d708b32025caf072a4310b972a47048f7653326c498fc42203</citedby><cites>FETCH-LOGICAL-c372t-1be06619cd1b815d708b32025caf072a4310b972a47048f7653326c498fc42203</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/257869$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23930,23931,25140,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/257869$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4050746$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Jain, V.K.</creatorcontrib><creatorcontrib>Wadekar, S.A.</creatorcontrib><creatorcontrib>Lei Lin</creatorcontrib><title>A universal nonlinear component and its application to WSI</title><title>IEEE transactions on components, hybrids, and manufacturing technology</title><addtitle>T-CHMT</addtitle><description>Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology.< ></description><subject>Applied sciences</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Coprocessors</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital signal processing chips</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Image processing</subject><subject>Integrated circuits</subject><subject>Interpolation</subject><subject>Read only memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Digital signal processing chips</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Image processing</topic><topic>Integrated circuits</topic><topic>Interpolation</topic><topic>Read only memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal processing</topic><topic>Signal processing algorithms</topic><topic>Wafer scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Jain, V.K.</creatorcontrib><creatorcontrib>Wadekar, S.A.</creatorcontrib><creatorcontrib>Lei Lin</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on components, hybrids, and manufacturing technology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jain, V.K.</au><au>Wadekar, S.A.</au><au>Lei Lin</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A universal nonlinear component and its application to WSI</atitle><jtitle>IEEE transactions on components, hybrids, and manufacturing technology</jtitle><stitle>T-CHMT</stitle><date>1993-11-01</date><risdate>1993</risdate><volume>16</volume><issue>7</issue><spage>656</spage><epage>664</epage><pages>656-664</pages><issn>0148-6411</issn><eissn>1558-3082</eissn><coden>ITTEDR</coden><abstract>Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/33.257869</doi><tpages>9</tpages></addata></record> |
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subjects | Applied sciences Clocks CMOS technology Coprocessors Design. Technologies. Operation analysis. Testing Digital signal processing chips Electronics Exact sciences and technology Image processing Integrated circuits Interpolation Read only memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing Signal processing algorithms Wafer scale integration |
title | A universal nonlinear component and its application to WSI |
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