An ASIC implementation of an optimized digital video encoder

This paper presents a design of an optimized video encoder using a simple pipelined architecture. The proposed video encoder accepts conventional NTSC/PAL video signals. It also processes the PALplus video signal using an improved decimation process. The proposed encoder requires only 25 K gates, wh...

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Veröffentlicht in:	IEEE transactions on consumer electronics 1998-08, Vol.44 (3), p.1097-1102
Hauptverfasser:	Oh, Seung-Ho, Han, Sun-Hyoung, Kang, Bongsoon, Lee, Moon Key
Format:	Artikel
Sprache:	eng
Schlagworte:	Application specific integrated circuits CMOS technology Design automation Design optimization Electronic mail Frequency Hardware Large scale integration Signal processing TV broadcasting
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