On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations
The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for...
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| Veröffentlicht in: | IEEE transactions on electron devices 1993-03, Vol.40 (3), p.525-541 |
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| container_end_page | 541 |
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| container_issue | 3 |
| container_start_page | 525 |
| container_title | IEEE transactions on electron devices |
| container_volume | 40 |
| creator | Cressler, J.D. Comfort, J.H. Crabbe, E.F. Patton, G.L. Stork, J.M.C. Sun, J.Y.-C. Meyerson, B.S. |
| description | The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided.< > |
| doi_str_mv | 10.1109/16.199358 |
| format | Article |
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I. Transistor DC design considerations</title><source>IEEE Electronic Library (IEL)</source><creator>Cressler, J.D. ; Comfort, J.H. ; Crabbe, E.F. ; Patton, G.L. ; Stork, J.M.C. ; Sun, J.Y.-C. ; Meyerson, B.S.</creator><creatorcontrib>Cressler, J.D. ; Comfort, J.H. ; Crabbe, E.F. ; Patton, G.L. ; Stork, J.M.C. ; Sun, J.Y.-C. ; Meyerson, B.S.</creatorcontrib><description>The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided.< ></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.199358</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Bipolar transistors ; Circuits ; Degradation ; Design optimization ; Electronics ; Exact sciences and technology ; Germanium silicon alloys ; Heterojunctions ; Logic ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon germanium ; Temperature ; Transconductance ; Transistors</subject><ispartof>IEEE transactions on electron devices, 1993-03, Vol.40 (3), p.525-541</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1886-9f73c8a2c0b06debe1bbb87cd7a0b5125162e304f538396bb097e3005602cfe83</citedby><cites>FETCH-LOGICAL-c1886-9f73c8a2c0b06debe1bbb87cd7a0b5125162e304f538396bb097e3005602cfe83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/199358$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/199358$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4608086$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Cressler, J.D.</creatorcontrib><creatorcontrib>Comfort, J.H.</creatorcontrib><creatorcontrib>Crabbe, E.F.</creatorcontrib><creatorcontrib>Patton, G.L.</creatorcontrib><creatorcontrib>Stork, J.M.C.</creatorcontrib><creatorcontrib>Sun, J.Y.-C.</creatorcontrib><creatorcontrib>Meyerson, B.S.</creatorcontrib><title>On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided.< ></description><subject>Applied sciences</subject><subject>Bipolar transistors</subject><subject>Circuits</subject><subject>Degradation</subject><subject>Design optimization</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Germanium silicon alloys</subject><subject>Heterojunctions</subject><subject>Logic</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon germanium</subject><subject>Temperature</subject><subject>Transconductance</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNpFkDtPwzAUhS0EEqUwsDJ5YGFIsPNw7BEVKIhKHVrmyHauW6M0juwMlB_C78U0PKaro_vdc3UOQpeUpJQScUtZSoXIS36EJrQsq0Swgh2jCSGUJyLn-Sk6C-EtSlYU2QR9Ljs8bAH33hnbAm4g2E2HZddg1w92Zz_kYF2HncHQ20G-W9nilU0OxMrOIVEyAFa2d630eAC97VzrNntsnMdVhV-w7PvW6oNNSPFzitdedsGGIQL3s9-POm5tA37kztGJkW2Ai585Ra-PD-vZU7JYzp9nd4tEU85ZIkyVay4zTRRhDSigSile6aaSRJU0KynLICeFKWNywZQiooqalIxk2gDPp-hm9NXeheDB1L23O-n3NSX1d6E1ZfVYaGSvR7aXQcvWxBTahr-DghFOOIvY1YhZAPi3Gz2-AA5dflY</recordid><startdate>199303</startdate><enddate>199303</enddate><creator>Cressler, J.D.</creator><creator>Comfort, J.H.</creator><creator>Crabbe, E.F.</creator><creator>Patton, G.L.</creator><creator>Stork, J.M.C.</creator><creator>Sun, J.Y.-C.</creator><creator>Meyerson, B.S.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>199303</creationdate><title>On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations</title><author>Cressler, J.D. ; Comfort, J.H. ; Crabbe, E.F. ; Patton, G.L. ; Stork, J.M.C. ; Sun, J.Y.-C. ; Meyerson, B.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1886-9f73c8a2c0b06debe1bbb87cd7a0b5125162e304f538396bb097e3005602cfe83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Bipolar transistors</topic><topic>Circuits</topic><topic>Degradation</topic><topic>Design optimization</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Germanium silicon alloys</topic><topic>Heterojunctions</topic><topic>Logic</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon germanium</topic><topic>Temperature</topic><topic>Transconductance</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Cressler, J.D.</creatorcontrib><creatorcontrib>Comfort, J.H.</creatorcontrib><creatorcontrib>Crabbe, E.F.</creatorcontrib><creatorcontrib>Patton, G.L.</creatorcontrib><creatorcontrib>Stork, J.M.C.</creatorcontrib><creatorcontrib>Sun, J.Y.-C.</creatorcontrib><creatorcontrib>Meyerson, B.S.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cressler, J.D.</au><au>Comfort, J.H.</au><au>Crabbe, E.F.</au><au>Patton, G.L.</au><au>Stork, J.M.C.</au><au>Sun, J.Y.-C.</au><au>Meyerson, B.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1993-03</date><risdate>1993</risdate><volume>40</volume><issue>3</issue><spage>525</spage><epage>541</epage><pages>525-541</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/16.199358</doi><tpages>17</tpages></addata></record> |
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| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1993-03, Vol.40 (3), p.525-541 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_crossref_primary_10_1109_16_199358 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Bipolar transistors Circuits Degradation Design optimization Electronics Exact sciences and technology Germanium silicon alloys Heterojunctions Logic Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon germanium Temperature Transconductance Transistors |
| title | On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations |
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