Delay analysis of high-electron mobility transistors under high drain bias

In this work, we present a new delay analysis of high-electron-mobility transistors (HEMTs), in which we show that the total intrinsic delay can be separated into six distinct contributions. We distinguish between delays caused by the capacitive coupling between electrodes, the quasi-static charge distribution within the device and a dynamic delay originating from on-state charge flow. An analytical expression for the dynamic delay is established in the form of a delay density using a position dependent image charge analysis. This delay density allows us to show graphically the position dependence of the delay contributions of mobile charge throughout the depletion region. Furthermore, the dynamic delay is separated into a component dependent on the length of the gate electrode and a drain delay component dependent on the drain voltage bias. The influence of high drain bias on the delay components is investigated with the aid of GaN HEMT device simulations and measurements, showing the relative importance of scaling the gate and the drain regions. The RF delay analysis reported here is based upon the definition of small-signal current gain and elucidates the effect of position dependent mobile charge within a HEMT, clarifying the requirements for device scaling.