Graphene field effect transistors with parylene gate dielectric
We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene fla...
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| Veröffentlicht in: | Applied physics letters 2009-12, Vol.95 (24), p.242104-242104-3 |
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| Sprache: | eng |
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| container_end_page | 242104-3 |
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| container_issue | 24 |
| container_start_page | 242104 |
| container_title | Applied physics letters |
| container_volume | 95 |
| creator | Sabri, S. S. Lévesque, P. L. Aguirre, C. M. Guillemette, J. Martel, R. Szkopek, T. |
| description | We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of
10
000
cm
2
/
Vs
at
10
12
/
cm
2
electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide. |
| doi_str_mv | 10.1063/1.3273396 |
| format | Article |
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10
000
cm
2
/
Vs
at
10
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/
cm
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electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/1.3273396</identifier><identifier>CODEN: APPLAB</identifier><language>eng</language><publisher>American Institute of Physics</publisher><ispartof>Applied physics letters, 2009-12, Vol.95 (24), p.242104-242104-3</ispartof><rights>2009 American Institute of Physics</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c284t-28a05f1fc02aeb2e8473d134588ec82ae165dfc1c3d2bff6cbb0fcd79f708adb3</citedby><cites>FETCH-LOGICAL-c284t-28a05f1fc02aeb2e8473d134588ec82ae165dfc1c3d2bff6cbb0fcd79f708adb3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://pubs.aip.org/apl/article-lookup/doi/10.1063/1.3273396$$EHTML$$P50$$Gscitation$$H</linktohtml><link.rule.ids>314,780,784,794,1559,4512,27924,27925,76384,76390</link.rule.ids></links><search><creatorcontrib>Sabri, S. S.</creatorcontrib><creatorcontrib>Lévesque, P. L.</creatorcontrib><creatorcontrib>Aguirre, C. M.</creatorcontrib><creatorcontrib>Guillemette, J.</creatorcontrib><creatorcontrib>Martel, R.</creatorcontrib><creatorcontrib>Szkopek, T.</creatorcontrib><title>Graphene field effect transistors with parylene gate dielectric</title><title>Applied physics letters</title><description>We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of
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Vs
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electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.</description><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><recordid>eNp1z0tLxDAQwPEgCtbVg98gVw9dM5k-0osii67Cghc9hzQPN1LbkgTEb2_24dFTmPBjmD8h18CWwBq8hSXyFrFrTkgBrG1LBBCnpGCMYdl0NZyTixg_81hzxILcr4Oat3a01Hk7GGqdszrRFNQYfUxTiPTbpy2dVfgZduxDJUtNtpkFry_JmVNDtFfHd0Henx7fVs_l5nX9snrYlJqLKpVcKFY7cJpxZXtuRdWiAaxqIawW-Q-a2jgNGg3vnWt03zOnTdu5lgllelyQm8NeHaYYg3VyDv4rHyWByV25BHksz_buYKP2SSU_jf_jv3y5z5f7fPwFPP1hrQ</recordid><startdate>20091214</startdate><enddate>20091214</enddate><creator>Sabri, S. S.</creator><creator>Lévesque, P. L.</creator><creator>Aguirre, C. M.</creator><creator>Guillemette, J.</creator><creator>Martel, R.</creator><creator>Szkopek, T.</creator><general>American Institute of Physics</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20091214</creationdate><title>Graphene field effect transistors with parylene gate dielectric</title><author>Sabri, S. S. ; Lévesque, P. L. ; Aguirre, C. M. ; Guillemette, J. ; Martel, R. ; Szkopek, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c284t-28a05f1fc02aeb2e8473d134588ec82ae165dfc1c3d2bff6cbb0fcd79f708adb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sabri, S. S.</creatorcontrib><creatorcontrib>Lévesque, P. L.</creatorcontrib><creatorcontrib>Aguirre, C. M.</creatorcontrib><creatorcontrib>Guillemette, J.</creatorcontrib><creatorcontrib>Martel, R.</creatorcontrib><creatorcontrib>Szkopek, T.</creatorcontrib><collection>CrossRef</collection><jtitle>Applied physics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Sabri, S. S.</au><au>Lévesque, P. L.</au><au>Aguirre, C. M.</au><au>Guillemette, J.</au><au>Martel, R.</au><au>Szkopek, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Graphene field effect transistors with parylene gate dielectric</atitle><jtitle>Applied physics letters</jtitle><date>2009-12-14</date><risdate>2009</risdate><volume>95</volume><issue>24</issue><spage>242104</spage><epage>242104-3</epage><pages>242104-242104-3</pages><issn>0003-6951</issn><eissn>1077-3118</eissn><coden>APPLAB</coden><abstract>We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of
10
000
cm
2
/
Vs
at
10
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cm
2
electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.</abstract><pub>American Institute of Physics</pub><doi>10.1063/1.3273396</doi></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0003-6951 |
| ispartof | Applied physics letters, 2009-12, Vol.95 (24), p.242104-242104-3 |
| issn | 0003-6951 1077-3118 |
| language | eng |
| recordid | cdi_crossref_primary_10_1063_1_3273396 |
| source | AIP Journals Complete; AIP Digital Archive; Alma/SFX Local Collection |
| title | Graphene field effect transistors with parylene gate dielectric |
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