Two-trap model for low voltage stress-induced leakage current in ultrathin SiON dielectrics

Stress-induced leakage current is a useful probe of the buildup of trap states created by the electrical stress of ultrathin dielectric films. The generation of both bulk and interface traps can affect the current-voltage characteristics. It has been shown that trap assisted tunneling through interface traps is the dominant transport mechanism below 3.5 nm thickness when the poststress leakage is sensed in the off state. However, there is some ambiguity in the literature regarding whether traps at one or both of the contact interfaces are involved in the tunneling process. In this work, we show that for n -channel metal-oxide-semiconductor (NMOS) devices, the off-state ( V G < 0 V ) gate current of electrically stressed ultrathin SiON dielectrics senses a two-trap tunneling process that involves interface states at both anode and cathode interfaces. In aggregate, five peaks due to tunneling via interface traps are observed in the poststress I - V characteristics of ultrathin NMOS SiON dielectrics.