Analysis of quantum ballistic electron transport in ultrasmall silicon devices including space-charge and geometric effects

A two-dimensional device simulation program which self consistently solves the Schrödinger and Poisson equations with current flow is described in detail. Significant approximations adopted in this work are the absence of scattering and a simple six-valley, parabolic band structure for silicon. A modified version of the quantum transmitting boundary method is used to describe open boundary conditions permitting current flow in device solutions far from equilibrium. The continuous energy spectrum of the system is discretized by temporarily imposing two different forms of closed boundary conditions, resulting in energies which sample the density-of-states and establish the wave function normalization conditions. These standing wave solutions (“normal modes”) are decomposed into their traveling wave constituents, each of which represents injection from only one of the open boundary contacts (“traveling eigencomponents”). These current-carrying states are occupied by a drifted Fermi distribution associated with their injecting contact and summed to form the electron density in the device. Holes are neglected in this calculation. The Poisson equation is solved on the same finite element computational mesh as the Schrödinger equation; devices of arbitrary geometry can be modeled. Computational performance of the program including characterization of a “Broyden+Newton” algorithm employed in the iteration for self consistency is described. Device results are presented for a narrow silicon resonant tunneling diode (RTD) and many variants of idealized silicon double-gate field effect transistors (DGFETs). The RTD results show two resonant conduction peaks, each of which demonstrates hysteresis. Three 7.5 nm channel length DGFET structures with identical intrinsic device configurations but differing access geometries (straight, taper and “dog bone”) are studied and found to have differing current flows owing to quantum-mechanical reflection in their access regions. Substantial gate-source overlap (10 nm) in these devices creates the possibility that the potential in the source can precipitously decrease for sufficiently high gate drive, which allows electron tunneling backwards through the channel from drain to source. A 7.5 nm gate length zero gate overlap taper device with 3 nm thick silicon channel is analyzed and internal distributions of device potential, electron density, velocity and current density are presented. As this device is scaled to 5 nm gate length,