Self-biased anti-parallel diode pair in 130-nm CMOS

This Letter presents a self-biased anti-parallel diode pair (APDP) in a 130-nm standard digital CMOS process. The proposed device employs complementary polysilicon-gate-separated Schottky barrier diodes (SBDs). A parallel RC network in series with the n-well of n-type SBD connected in shunt is used...

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Veröffentlicht in:	Electronics letters 2016-06, Vol.52 (13), p.1147-1149
Hauptverfasser:	Shim, D, O, K.K
Format:	Artikel
Sprache:	eng
Schlagworte:	Accumulation Automation cathode‐tied C‐APDP CMOS CMOS digital integrated circuits complementary polysilicon‐gate‐separated Schottky barrier diodes cutoff frequency Devices Diodes Electronics harmonic power measurements Harmonics input power level I‐V curve Level (quantity) Microwave technology n‐type SBD output harmonic power generation parallel RC network RC circuits SBDs Schottky diodes self‐bias voltage self‐biased anti‐parallel diode pair self‐biased complementary‐APDP size 130 nm standard digital CMOS process
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