Synaptic array using multi-level AND flash memory cells for hardware-based neural networks

•We propose an AND array architecture in which bit-lines (BLs) and source-lines (SLs) of thin film transistor (TFT)-type flash memory cells used as synapses are arranged in parallel, and show the fabricated device and array characteristics.•A top gate dielectric stack and a bottom gate dielectric stack serve to store a synaptic weight and select excitatory or inhibitory synapses, respectively.•Multi-level (>5-bit) synaptic weight states and selective write operations in the AND array architecture are achieved by utilizing a simple update pulse scheme.•Furthermore, weighted sum operation in a fabricated 9 × 3 AND flash synaptic array is successfully carried out by measuring BL currents when input pulses are applied to multiple word-lines (WLs) for hardware-based neural networks (HNNs). We propose an AND array architecture in which bit-lines (BLs) and source-lines (SLs) of thin film transistor (TFT)-type flash memory cells used as synapses are arranged in parallel, and show the fabricated device and array characteristics. A top gate dielectric stack and a bottom gate dielectric stack serve to store a synaptic weight and select excitatory or inhibitory synapses, respectively. Multi-level (>5-bit) synaptic weight states and selective write operations in the AND array architecture are achieved by utilizing a simple update pulse scheme. Furthermore, weighted sum operation in a fabricated 9 × 3 AND flash synaptic array is successfully carried out by measuring BL currents when input pulses are applied to multiple word-lines (WLs) for hardware-based neural networks (HNNs).